Teams at Kandou AI

Design and prototype FPGA blocks for high-speed PHY/SerDes IP and multi-Gigabit data-link transceivers. Validate and bring up devices and FPGAs in the laboratory, collaborate with firmware, digital, verification, and lab teams, and use RTL, scripting, and industry-standard FPGA tools for design validation, simulation, and verification.

Looking for circuit designers specializing in SerDes with HF frequency experience and Precision LF with DC circuit implementation at 5nm nodes.