Teams at Kandou AI

Design and prototype FPGA blocks for high-speed PHY/SerDes IP and multi-Gigabit data-link transceivers. Validate and bring up devices and FPGAs in the laboratory, collaborate with firmware, digital, verification, and lab teams, and use RTL, scripting, and industry-standard FPGA tools for design validation, simulation, and verification.

Lead the signal integrity and power integrity function, guiding architecture, resolving system challenges, and collaborating on robust solutions for AI hardware.

Design and implement DFT solutions including hierarchical MBIST and scan insertion, ATPG pattern generation and coverage convergence, timing-aware pattern simulation, IJTAG cycle-accurate functional patterns, and debug silicon with test and production teams through probe and final test.