Teams at Intel

Lead pre-silicon SoC verification for graphics frontend: develop SystemVerilog/UVM testbenches, create constrained-random and directed tests, run simulation and emulation, debug RTL/testbench failures, close functional/code/assertion coverage, document verification plans, collaborate with architecture and post-silicon teams, mentor juniors, and improve verification methodology and automation.

Perform functional verification of IP and sub-systems: develop verification plans, testbenches and environments; run system simulations to verify microarchitecture, power, and timing; reproduce and debug pre-silicon issues; implement fixes; collaborate with architects, RTL and physical design teams; document test plans and improve verification infrastructure and methodology.

Develop and execute IP-level verification plans, build and maintain testbenches and UVM/OVM environments, run functional/system simulations, debug failures, analyze power/timing impacts, document results, and collaborate with architects, RTL and physical design teams to improve verification frameworks and infrastructure.