Intel

HQ
Santa Clara
Total Offices: 39
75,000 Total Employees
Year Founded: 1968

Intel Benefits Overview

Compensation + Benefits

Offers 401(K)

Offers life insurance

Provides a pension

Offers occupational accident insurance

Offers retiree health & medical

Offers disability insurance

Offers charitable contribution matching

Offers supplemental life insurance

Offers accidental death & dismemberment insurance

Provides adoption assistance

Provides family medical leave

Provides fertility benefits

Offers childcare benefits

Offers generous parental leave

Offers company equity

Offers performance bonuses

Offers employee stock purchase plan

Offers employee discounts

Offers dental insurance

Offers health insurance

Offers mental health benefits

Offers dependent care

Offers Flexible Spending Account (FSA)

Offers vision insurance

Offers Health Savings Account (HSA)

Offers healthcare on-site

Company Culture

Provides commuter benefits

Offers travel concierge services

Provides a mobile phone discount

Offers legal assistance

Utilizes a flexible work schedule

Offers a remote work program

Offers diversity-based Employee Resource Groups

Work-Life Balance + Wellbeing

Offers company-sponsored outings

Offers gym membership

Offers an Employee Assistance Program (EAP)

Offers generous PTO

Provides paid holidays

Offers sabbatical leave

Provides military leave

Offers paid volunteer time

Provides paid sick days

Provides bereavement leave

Offers unpaid extended leave

Career Growth + Development

Provides customized development tracks

Job training & conferences

Provides tuition assistance

Offers apprenticeship programs

Recently posted jobs

An Hour AgoSaved
In-Office
2 Locations
Artificial Intelligence • Cloud • Information Technology • Software
Participate in RTL functional validation and VLSI/CMOS design for next-generation SoC/CPU. Develop structural physical design flows (synthesis, floorplanning, P/G, CTS, P&R, RC-extraction), design analog IP (PLLs, DLLs, bandgap, IO, DDR), integrate third-party IP, and perform pre/post-silicon debug and system integration across memory and peripheral interfaces.
An Hour AgoSaved
In-Office
3 Locations
Artificial Intelligence • Cloud • Information Technology • Software
Lead physical design timing efforts for next-generation SoCs: perform timing analysis and optimization, generate and validate timing constraints, define PVT conditions, develop timing models and flows, collaborate with clocking, architecture, and logic teams to ensure high-performance, low-power chip integration.
3 Hours AgoSaved
In-Office
2 Locations
Artificial Intelligence • Cloud • Information Technology • Software
Design and debug CPU circuits at the transistor level, optimize designs, and collaborate with teams to meet power and performance targets.