Search the 16 jobs at InnoPhase IoT

The Staff/Sr. Staff Engineer, RF PLL Design will lead the development of custom RF, analog, and mixed signal IPs. Responsibilities include hands-on design of high-performance RF synthesizers, supervising layout activities, collaborating with cross-functional teams, and presenting findings to management. The role also involves validating methods to alleviate circuit impairments and participating in post-silicon performance characterization.

The Principal Engineer will lead the development of RF, analog, and mixed signal IPs for SoC products. Responsibilities include designing RF frequency synthesizers, supervising layout activities, collaborating with cross-functional teams, conducting simulations, and aiding in test plan design and validation.

The Principal Engineer, RFIC Design will lead and contribute to the design and development of high-performance RFICs and mixed signal IPs, oversee layout activities, and work across various teams to ensure product specifications are met, along with conducting simulations and post-silicon testing.

The Staff/Sr. Staff Engineer, RFIC Design will lead the design of custom RF, analog, and mixed signal ICs, supervising layout activities, running simulations, collaborating with cross-functional engineers, and assisting test engineers in production ramp-up. The role requires hands-on technical leadership and contributions to high-performance connectivity products.

The Senior Staff DFT Engineer at InnoPhase IoT will architect and support DFT for IoT products, using DFT/ATPG/MBIST tools for SOCs. Responsibilities include developing DFT plans, ensuring manufacturing quality, assisting the design team with low-power constraints, debugging, and vector generation.

The Staff Software Engineer at InnoPhase IoT will design and implement security features for IoT products, analyze and fix vulnerabilities, integrate security tools, and support customer trials. The role involves driving innovation and testing firmware in embedded systems, with a focus on security and modular designs.

As a PHY Verification Engineer, you will design and develop UVM testbenches for wireless PHY layers and work collaboratively with design and system engineers to identify and resolve verification bottlenecks.

The Senior Software Test & Automation Engineer designs, develops, and executes test software solutions for WiFi SOC and radio debug and automated test solutions specifically for the IoT market. Responsibilities include collaborating with various teams, developing test cases and documentation, and creating debug tools, ensuring high-quality outputs and effective communication within multi-functional teams.

The Principal Engineer will lead the development of integrated custom analog and mixed signal IPs, focusing on high-performance ADC design. Responsibilities include supervising design teams, conducting layout activities, performing simulations, and collaborating with cross-functional engineers to meet product specifications and ensure quality.

The Principal Software Engineer will design, develop, and lead the architecture of embedded wireless firmware for IoT products, focusing on ULP solutions. Responsibilities include developing drivers, collaborating with a global team, and ensuring timely delivery of high-quality products.

The PHY Design Engineer will design low-power communication systems and develop micro-architecture and SystemVerilog RTL. Responsibilities include collaborating on product specifications, design verification, identifying bottlenecks, and providing guidance to teams on physical design and timing closure.

The Principal PHY/MAC RTL Design Engineer will be responsible for implementing MAC and PHY algorithms for low power IoT connectivity devices, developing specifications, creating micro-architecture in Verilog/Systemverilog, verifying designs, and collaborating with cross-functional teams.

As a PHY Verification Engineer/Lead at InnoPhase IoT, you will define and develop UVM testbenches for wireless PHY and MAC layers, collaborating with design and system engineers. Responsibilities include optimizing test plans, conducting verification coverage analysis, running regressions, and refining verification tools. Your role also involves debugging and problem-solving in a team environment.

As a PHY Design Engineer/Lead, you will be responsible for developing low-power WiFi and BT/BLE micro-architecture and RTL design. You will work on digital signal processing engines, analyze design bottlenecks, and collaborate with verification teams on test plans and design tools.

Design and execute physical design implementation of low-power and high-performance SoC in advanced technology nodes. Responsible for logic synthesis, floor planning, power planning, place & route, timing closure, and physical verification. Collaborate with cross-functional teams and vendors to drive design modifications and enhance automation.

Lead the physical design implementation of low-power and high-performance SoC in advanced technology nodes. Collaborate with RTL and System design teams, automate workflows, and drive tool improvements. Bachelor's degree in Electrical Engineering required.