Teams at Exegy

Participate in the full software development lifecycle for high-performance, low-latency financial data processing applications. Responsibilities include software design, development, testing, secure coding, version control, adopting new technologies, and completing projects collaboratively. The intern will work with Python, C, C++, Linux, GitLab, Jenkins, Artifactory, Jira, Agile, and CI/CD practices in a hybrid St. Louis environment.

The Senior Network Engineer will support Exegy's network infrastructure, including administration, device maintenance, and collaboration with vendors for troubleshooting and changes.

Design, implement, verify, and optimize ultra-low-latency FPGA logic and reusable HDL building blocks. Own RTL development (VHDL/Verilog), timing closure, simulation, synthesis, board bring-up, hardware validation, and test automation using Python/Linux. Implement networking and system protocols (TCP/UDP, Ethernet MAC/PCS, PCIe, DMA). Mentor engineers, perform design reviews, and collaborate with architects, software, and product teams to deliver maintainable, high-performance FPGA solutions.