Teams at Etched

Lead board-level NPI for ASIC accelerator hardware from design freeze through EVT/DVT/PVT and volume ramp. Own schedules, risks, CM coordination, BOM/AVL readiness, ECO tracking, manufacturing readiness, test strategy, yield tracking, KPI reporting, and cross-functional alignment with engineering and supply chain.

The DFT Engineer ensures efficient testability of ICs, develops DFT architectures, verifies implementations, and collaborates with teams for optimal production support.

Design and optimize AI accelerator architectures focusing on performance and efficiency for transformer workloads. Collaborate cross-functionally on innovative chip designs.