Search the 18 jobs at Etched

The role involves defining the technical roadmap for AI chip products, gathering customer feedback, providing technical insights during sales interactions, and collaborating with engineering teams to align product capabilities with customer needs. The ideal candidate should be personable, proactive, and have a strong understanding of AI chips and customer-facing roles.

The Reliability Engineer will ensure that components and systems meet reliability standards essential for datacenter applications. Responsibilities include developing reliability standards, collaborating on component selection, evaluating testing plans, analyzing reliability data, and working with suppliers to enhance performance and maintain quality standards.

As a Software Engineer focusing on Infrastructure Performance, you'll design and write software for ASICs, ensuring CI tests run efficiently, scoping tools, and provisioning new servers. You'll automate IT processes and improve performance for upcoming chips while collaborating with the IT team on networking and setup.

As a DRAM Engineer at Etched, you will optimize memory controllers and PHYs, conduct DRAM simulations, validate SoC memory integration, and oversee HBM silicon testing while developing debugging methodologies and ensuring performance and reliability specifications are met.

The Technical Program Manager at Etched will oversee the collaboration between internal teams and external vendors to ensure successful delivery of AI datacenter hardware projects. Responsibilities include managing timelines, identifying risks, enhancing operational efficiency, and using KPIs for project success. The role demands exceptional leadership and communication skills, along with a solid understanding of hardware and ASIC design.

The Firmware Engineer will develop and optimize firmware for high-speed interface IPs like PCIe and HBM, conduct debugging and validation in simulation and silicon environments, collaborate with hardware engineers, and propose enhancements for future interface generations.

As a Technical Recruiter at Etched, you will manage the full-cycle recruitment process to attract top talent in the AI industry. Collaborating with hiring managers, you will improve candidate experience and explore unconventional sourcing methods to find exceptional candidates. Additionally, you will facilitate interviews, manage the offer process, and contribute to enhancing recruitment strategies.

The Power Supply Integration Engineer will design and develop advanced power supply solutions for high-power processors, focus on multi-phase power solutions, handle 48V input conversion, conduct PCB analysis, and collaborate with vendors to ensure optimal performance. Responsibilities include testing, validation, and maintaining design documentation.

The Rack Level Integration Engineer will oversee the selection, qualification, and integration of components within data center racks, including servers, networking equipment, and cooling solutions. Responsibilities include managing water cooling systems, hands-on lab setup, and documenting integration processes while collaborating with cross-functional teams for optimal performance.

As an RTL Design Engineer at Etched, you will develop and implement design verification strategies for AI chips, ensuring correct and efficient operation. You will work with high-speed digital logic and contribute to projects involving floating-point math computation and timing constraints, while also learning about modern AI architectures.

The Senior Layout PCB Engineer will design and optimize high-speed PCBs using Cadence Allegro, focusing on 100G signaling, power distribution, and HDI stack-ups for data center products. Responsibilities include leading PCB layout projects, developing power networks, and collaborating with engineering teams for system integration to ensure performance and manufacturability.

As a Procurement professional at Etched, you will manage vendor relationships, expedite purchasing processes, and ensure timely materials delivery for production. You'll create systems for tracking orders, negotiate contracts, and evaluate suppliers to optimize the procurement function.

The Physical Design Engineer will manage outsourcing for physical design, verify designs, and improve iteration speed. Responsibilities include overseeing design flows, optimizing tool usage, and facilitating block-level closure while collaborating with EDA vendors and supporting the ASIC infrastructure.

The Principal Design Verification Engineer will develop ASIC testbenches, implement micro-architecture using System Verilog, and collaborate with design teams to ensure microchip functionality. Responsibilities include executing functional verification, applying timing closure methods, utilizing formal verification tools, debugging designs, and documenting the verification process.

The Firmware Engineer will design, implement, and optimize firmware for AI accelerator systems, conduct debugging and validation in various environments, and collaborate with hardware engineers to enhance performance. Key responsibilities include firmware development for RTOS embedded systems and proposing improvements for future AI accelerator generations.

The Design Verification Engineer will ensure the successful development of test benches for Etched's first ASIC, focusing on scalable testing methods. They will work closely with the engineering team to guarantee deliverables meet quality and performance standards while being passionate about modern AI technologies.

The People Operations Associate will manage payroll, benefits administration, and daily office operations. Responsibilities include processing payroll, overseeing employee benefits, maintaining HRIS systems, and providing general HR support to the team.

The Principal Physical Design Engineer at Etched will oversee 3rd party design services, optimize physical design tool flows, and drive project convergence dashboards while ensuring backend design and timing closure. The role requires experience in low power design methodologies and familiarity with automated RTL-to-GDSII flows.