The RTL Design Engineer will develop verification strategies for ASIC designs, focusing on machine learning and digital logic, requiring at least 5 years of experience.

The role involves financial modeling, creating P&L and cash flow models, establishing accounting systems, and optimizing working capital while collaborating with the executive team to drive initiatives.

Lead all legal operations at Etched, focusing on commercial agreements, corporate governance, and compliance while supporting growth and strategic partnerships.

Develop power models and optimize chip power consumption while collaborating with engineers. Analyze data to enhance efficiency pre and post silicon.

Optimize RTL designs for power efficiency, perform power analysis during silicon design, and collaborate with the physical design team to meet power targets.

As an Inference Software Engineer, you will contribute to software architecture, implement high-performance code, and interface with cross-functional teams to optimize AI model inference.

Conduct research to optimize AI chip performance, translating mathematical operations for Sohu’s architecture, and enhancing model efficiency through collaboration with hardware architects.

Seeking experienced IC Package Engineer to drive substrate layout and package design, ensuring mechanical and electrical integrity for AI hardware packages.

Manage and maintain ECAD/MCAD libraries, ensuring integration between electrical and mechanical designs while supporting DFM requirements and compliance.

Develop and own SoC functional models, collaborate with teams on integration, optimize infrastructure performance, and simulate AI models on ASIC architecture.

Join Etched.ai as a Senior Firmware Engineer, optimizing Sohu chip software, collaborating with experts, and solving complex AI challenges.

The Firmware Engineer will develop software optimized for large transformer AI models, tackling challenges from low-level drivers to high-level applications, and contribute to revolutionary AI solutions.

As a Design Infrastructure Engineer, you will build and maintain design processes for custom silicon products, manage workflows, ensure design quality, and support cross-functional collaboration.

The ASIC Timing Engineer will perform timing analysis and closure for AI chips, collaborate across teams on strategies, and enhance timing convergence flows.

The Reliability Engineer ensures system and component reliability standards for datacenter applications, collaborating with suppliers and cross-functional teams.

As a Mechanical Engineer, you will develop high-power data center products from concept to production, ensuring robust designs that meet strict performance and manufacturability standards.

The Physical Design Engineer will manage physical designs, optimize design flows, and collaborate with 3rd party services, focusing on ASICs.

The role involves designing and optimizing high-speed PCB layouts for data center products using Cadence Allegro tools, focusing on performance and reliability.

The Core Operations role involves leading critical initiatives, facilitating leadership decision-making, driving cross-functional collaboration, and establishing operational metrics to ensure organizational performance and strategic alignment.

Lead PCB layout and design operations, develop a scalable design infrastructure, and manage a high-performing team of PCB layout engineers and ECAD librarians, ensuring quality and compliance.