Jobs at Etched

As an Accelerator Software Engineer, you will develop firmware and software for an ASIC, collaborating on design and implementation across multiple domains, including host-side drivers and microcontroller architecture.

The Infrastructure Intern will assist in developing infrastructure tooling for high-performance computing, supporting software engineering teams, and enhancing AI performance through effective collaboration and tools.

As a Design Verification intern at Etched, you'll validate custom IPs for chip performance and correctness, collaborating with various technical teams.

As an Inference Intern, you will support model porting, enhance runtime systems, optimize routing layers, and implement high-performance software for AI architectures.

As an RTL Intern, you will design microarchitecture and implement logic in Verilog, contribute to RTL development, and engage in the design cycle.

The role involves leading design for manufacturing initiatives, collaborating with suppliers, qualifying production processes, and ensuring high-quality mechanical components production.

The Finance Intern will support financial operations, execute financial models, assist in accounting, and collaborate with the executive team on strategic financial challenges.

Develop performance models for AI chips, analyze deep learning workloads, optimize hardware-software co-design, and collaborate on architectural decisions for efficiency.

Lead system-level reliability for Etched's servers, racks, and datacenter platforms. Define reliability strategy, qualification gates, accelerated and environmental testing, failure analysis, and reliability modeling (MTBF, Weibull, FIT). Build telemetry, fleet feedback, and validation processes; drive cross-functional root-cause investigations; enforce ODM/JDM reliability commitments; and hire and lead a product reliability engineering organization to ensure enterprise-grade field reliability.

Design and optimize AI accelerator architectures focusing on performance and efficiency for transformer workloads. Collaborate cross-functionally on innovative chip designs.

You will port models to new architectures, optimize runtime and communication layers, and develop performance profiling tools for inference operations.

The Technical Recruiter will manage the full-cycle recruiting process for technical talent, partner with hiring managers, source candidates creatively, and enhance recruiting workflows.

Ensure first silicon delivery for ASICs, develop test benches, and possess experience in hardware verification and scripting languages.

The Physical Design Engineer will oversee physical design implementations, optimize CAD infrastructures, and drive project convergence through dashboards, focusing on design methodologies and flows from RTL to GDSII.

The Senior Layout PCB Engineer will design and optimize PCBs for high-speed applications, focusing on signaling, power distribution, and complex HDI stack-ups, while collaborating with teams to enhance performance and manufacturability.

Lead board-level NPI for ASIC accelerator hardware from design freeze through EVT/DVT/PVT and volume ramp. Own schedules, risks, CM coordination, BOM/AVL readiness, ECO tracking, manufacturing readiness, test strategy, yield tracking, KPI reporting, and cross-functional alignment with engineering and supply chain.

Lead the development of system software for AI chips, manage software engineers, ensure high-performance ML platforms, and foster team growth.

Build critical infrastructure and custom applications, collaborate cross-functionally, and address operational challenges with a strong focus on delivering production-level code rapidly.

Work with package, PCB, ASIC, and system engineers to analyze high-speed interfaces (PCIe, Ethernet, SerDes), extract and validate S-parameter models, build HFSS 3D EM models, correlate simulation with lab measurements, and recommend design improvements to improve signal and power integrity across accelerator platforms.

Lead formal verification for complex ASIC IP and SoC subsystems. Define strategy, write SVA properties, build reusable formal environments, drive proof convergence, debug RTL/protocol bugs with formal counterexamples, and collaborate with architects, RTL, UVM DV, emulation, software, and firmware teams toward formal sign-off.