Jobs at Etched

Lead and scale Etched’s legal function, including team development, legal operations, contract processes, automation, complex commercial negotiations, corporate governance, financings, and IPO preparation. Advise executives and the board on strategic transactions, equity, compliance, intellectual property, employment, and disputes. Manage legal budgets and outside counsel while partnering with engineering, manufacturing, finance, and commercial teams across U.S. and international operations.

Manage end-to-end semiconductor production planning, scheduling, capacity forecasting, procurement, supplier coordination, and logistics across wafers, packaging, assembly, and test. Partner with foundries, OSATs, engineering, validation, and internal operations teams to support engineering builds and mass-production ramp. Build forecasts, dashboards, and executive reports while mitigating supply, test infrastructure, and manufacturing bottlenecks.

Build AI agents that autonomously design, simulate, evaluate, and improve electrical and mechanical hardware from requirements through manufacturable outputs. Integrate CAD, EDA, and simulation tools; develop engineering representations, evaluations, datasets, feedback systems, and reproducible experiment infrastructure. Collaborate with electrical, mechanical, and manufacturing teams to ship agent-generated designs and measure improvements in design cycle time, hardware performance, and engineering effort.

Lead Etched’s physical-world brand experiences, including conferences, recruiting events, product launches, investor events, internal gatherings, and speaker programs. Own events end to end across creative direction, production, logistics, vendors, budgets, and measurement. Partner with founders, creatives, recruiters, engineers, agencies, and external partners to deliver polished, memorable experiences aligned with recruiting, brand, and business goals.

Manage and maintain Allegro schematic symbol and PCB footprint libraries. Create and validate components, metadata, and manufacturing data while ensuring IPC, JEDEC, DFM, and compliance standards. Collaborate with electrical engineering, layout, manufacturing, and suppliers to resolve library issues, improve manufacturability, and prevent fabrication errors. Establish version control, approval, quality assurance, and data-integrity practices, using scripting to automate library management.

Design and optimize high-speed PCB layouts for 100G data center hardware using Cadence Allegro. Responsibilities include signal integrity, impedance control, crosstalk mitigation, power distribution network design, thermal management, complex HDI stack-ups, BGA breakouts, and collaboration with electrical and mechanical engineering teams to ensure performance and manufacturability.

As an RTL Intern, you will design microarchitecture and implement logic in Verilog, contribute to RTL development, and engage in the design cycle.

Designs complex IC substrate packages for high-power AI processors and accelerators. Responsibilities include large multi-layer substrate layouts, power delivery networks exceeding 700W, high-speed signaling above 50GHz, CoWoS interposer optimization, SI/PI collaboration, DRC and LVS verification, manufacturability support, documentation, design reviews, and technical guidance for junior engineers.

Support People Operations and Legal through compliance audits, employee records review, filings, contracts, onboarding and offboarding, recruiting handoffs, process documentation, and cross-functional company projects. The intern will investigate discrepancies, organize sensitive information, research requirements, coordinate across teams, and drive time-sensitive operational work to completion in a fully in-person San Jose office.

Build and deploy production-level solutions for Etched’s critical engineering challenges. Projects may include internal hardware tools, manufacturing execution systems, or agentic AI systems for R&D. The intern will own a project from scoping through production, working across full-stack engineering, infrastructure, and product development in a fast-paced, ambiguous environment.

Perform hands-on lab operations for frontier AI hardware, including running test stations, assembling and reworking hardware, cabling racks, managing inventory, and maintaining reliable day-to-day test operations. The role is fully in-person in San Jose, includes repetitive precision work, and may involve evening or weekend availability. Interns may take on engineering work over time.

Designs complex IC substrate packages for high-power AI processors and accelerators, including large multilayer layouts, dense routing, power delivery networks, and signaling beyond 50GHz. The role optimizes CoWoS interposer designs, performs DRC and LVS verification, collaborates with silicon, SI/PI, packaging, and manufacturing teams, and supports design reviews and technical guidance for junior engineers.

Manage and maintain Allegro schematic symbol and PCB footprint libraries. Create, validate, and organize accurate, manufacturable ECAD components; maintain metadata, part numbering, approvals, and datasheet links. Collaborate with electrical, layout, manufacturing, and supplier teams to resolve library issues, meet IPC, JEDEC, and DFM requirements, and improve fabrication yield. Perform quality checks and use version control and SKILL scripting to preserve data integrity and automate library tasks.

Own block- and subsystem-level physical design from RTL synthesis through GDSII sign-off. Perform floorplanning, placement, CTS, routing, timing closure, sign-off (EM/IR/RC/DRC/LVS), generate abstracts for hierarchical integration, improve PPA with RTL collaboration, and supervise third-party delivery.

Design and validate power delivery networks for high-current ASIC systems: perform PDN pre/post-layout analysis, DC IR-drop and AC impedance simulations, VRM modeling, thermal co-simulation, DRC/PI checks, bring-up debug, and maintain simulation-to-hardware correlation.

The Physical Design Engineer will focus on block-level implementation, timing closure, PPA optimization, and supervising outsourced design work while improving design flows.

The Technical Program Manager will oversee program delivery, align teams, manage vendor relationships, and optimize processes in the Infrastructure organization.

The Design Verification Engineer will lead IP subsystem verification, develop UVM/SystemVerilog environments, and collaborate with cross-functional teams to validate hardware-software performance.

As a Design Verification Engineer, you will collaborate with architects and RTL designers to verify designs, develop test plans and infrastructure, ensure performance, and debug issues across the hardware-software stack.

Lead technical accounting and external financial reporting: implement ASC 606/IFRS 15 revenue policies, own NetSuite ARM implementation, draft technical memos, advise on inventory, warranty, equity reporting, prepare external statements and disclosures, strengthen controls, and build/manage a revenue/technical accounting team.