Teams at Epia Neuro

Own the architecture, transistor-level design, verification, tapeout, and silicon bring-up of a low-noise, ultra-low-power analog/mixed-signal ASIC for an implantable neural interface. Lead foundry, IP, packaging, and test decisions; design critical analog blocks; develop behavioral models; direct verification and reliability analysis; mentor engineers; and establish design documentation and reproducibility standards.

Designs and documents ASIC modules, supports pre-silicon simulation and verification, develops hardware and software test systems, and validates and characterizes chips. The engineer will document test plans, debug root causes, and work across analog, digital, and post-silicon validation activities in an on-site startup environment.

Lead architecture and delivery of clinician-facing and patient-facing Android applications for neural interfaces and powered exoskeletons. Build real-time streaming data visualizations, device connectivity, cloud integrations, and safety features. Develop within IEC 62304 and FDA-regulated processes, producing documentation for audits and submissions. Partner with medical teams, translate user feedback into designs, and direct external contributors while ensuring accessibility, compliance, and integration quality.