Teams at Elevate Semiconductor

Lead architecture, design, simulation, and validation of high-speed precision CMOS ATE analog circuits. Own blocks through layout, verification, and post-layout analysis. Drive mixed-signal simulation strategy, mentor engineers, and collaborate with test, applications, and manufacturing to deliver robust silicon.

Lead analog architecture for ATE ICs, mentor engineers, drive innovations in circuit techniques, oversee design processes, and collaborate with stakeholders to achieve technical excellence.

Lead NPI from first silicon to high-volume manufacturing for precision analog and mixed-signal ICs. Develop and optimize wafer sort and final test solutions (Teradyne UltraFlex IGXL), correlate bench and ATE results, establish production limits, design/validate test hardware (load boards, probe cards, sockets), perform silicon debug/root-cause analysis, support qualification and transfer to OSAT, and create automation tools using Python and JMP to improve throughput and quality.