Teams at Efficient Computer

Design, integrate, and sign off synthesizable RTL for ultra-low-power SoC blocks, including compute fabric interconnects, memory interfaces, peripherals, low-power logic, and power-management systems. Own front-end quality through lint, CDC/RDC, LEC, synthesis, timing, and power analysis. Support verification, gate-level debugging, physical-design closure, tapeout, and silicon bring-up while collaborating with architecture, DV, physical design, and firmware teams.

Own verification for complex SoC blocks and subsystems from specification review through coverage sign-off. Build and extend UVM/SystemVerilog environments, develop assertions and coverage models, debug simulations, drive coverage closure, report verification risks, and document environments. The role requires extensive ASIC/SoC verification experience, strong scripting skills, independent execution, and collaboration with RTL designers and architects. Preferred experience includes C/C++, formal verification, AI-assisted verification, computer architecture, ML accelerators, and power-aware verification.

Own the Linux user-mode runtime, driver, and HAL interfaces for a Fabric accelerator. Responsibilities include runtime library design, compiler and kernel-driver integration, memory and resource management, ML framework backends, pre-silicon bring-up using simulation, emulation, QEMU, and FPGAs, and comprehensive runtime testing. Collaborate across compiler, architecture, verification, and kernel teams to support first-silicon deployment.