Delos Data Benefits Overview

Design and implement production-ready RTL for complex digital subsystems, translating architectural specifications into scalable microarchitectures. Collaborate with architecture, verification, and physical design teams on correctness, synthesis, timing, power, and area closure. Perform linting, CDC analysis, simulation, debug, integration, and design reviews. Contribute to reusable RTL, design methodologies, tooling, and AI-assisted workflows.

Develop and maintain RTL verification environments for ASIC and FPGA designs using UVM and SystemVerilog. Create coverage-driven plans, directed and constrained-random tests, assertions, and reusable verification components. Analyze simulations, debug design issues, track functional and code coverage, automate regressions with Python, and drive verification through closure. Collaborate with RTL engineers on reviews, testability, and reliable silicon delivery while verifying protocols including AXI, APB, PCIe, Ethernet, SPI, and I²C.

Build and maintain automated testing frameworks for distributed AI training and inference workloads. Develop end-to-end integration and stress-testing plans, validate GPU and hardware-software interactions, and troubleshoot failures in large-scale distributed systems. Partner with system engineers using telemetry and profiling tools to identify bottlenecks. The role requires Python, test automation, containerization, CI/CD, and familiarity with infrastructure management tools.