Teams at Ciena

Lead chip-level verification for complex FPGA designs by establishing verification methodologies, architectures, and infrastructure. Develop testbenches, models, generators, monitors, scoreboards, verification plans, and test cases using SystemVerilog and UVM. Analyze coverage, triage regressions, report defects, and drive bug resolution. Collaborate with design teams, establish priorities, and mentor junior verification engineers.

Three-year rotational Finance Development Program preparing early-career professionals for finance leadership roles. Participants rotate through accounting, FP&A, commercial management, tax, treasury, internal audit, and investor relations while supporting financial analysis, forecasting, reporting, business decisions, internal controls, and cross-functional improvement projects. The program emphasizes mentorship, networking, leadership development, data analysis, and applying AI and automation to improve financial processes.

Leads a team developing high-speed analog layouts for advanced CMOS and BiCMOS technologies, including SERDES, DAC, ADC, optical interface, and precision analog circuits. Responsibilities include floor planning, layout optimization, physical verification, electromigration and PERC checks, flow automation, methodology development, project delivery, cross-functional collaboration, and mentoring junior staff.