Teams at Cadence Design Systems

Develop and optimize high-performance, multi-threaded software for physical synthesis and routing in digital IC design. Responsibilities include algorithm research, C/C++ development on Linux, distributed-system debugging, performance optimization, and collaboration with global R&D and product engineering teams. The role supports advanced semiconductor design flows and may involve GPU programming, scripting automation, timing analysis, and EDA tools.

Internship opportunity at Cadence focused on developing future leaders and innovators in technology. The specific responsibilities and qualifications are not provided.

Lead execution of ASIC/SoC synthesis, logic equivalence checking, low-power verification, and power-intent flows. The role involves debugging Genus and Conformal issues, resolving constraint mismatches, supporting CLP sign-off, developing ECO scripts and timing/power constraints, and collaborating with physical design, DFT, and RTL teams. Candidates need 4–7 years of relevant experience, Cadence tool expertise, UPF/CPF knowledge, scripting skills, digital design fundamentals, STA understanding, and strong independent problem-solving abilities.