Teams at Cadence Design Systems

Define and implement SoC-level DFT architecture, perform DFT insertion, verification, and coverage analysis, drive pre-silicon DFT sign-off, and support post-silicon debug and yield learning while collaborating across RTL, verification, physical design, and operations teams.

Design and implement advanced algorithms to improve scalability and throughput of extraction processes. Maintain and extend existing C++ codebases, use basic scripting and AI coding tools, and collaborate with R&D, Foundry, and QA to deliver features that meet customer requirements.

Partner with R&D to identify and scope opportunities for Cadence's functional logic verification platform. Plan, execute, and manage technical evaluations with current and prospective customers; report progress to management and team. Train and ramp up customers and support customer projects.