Teams at Cadence Design Systems

Develop compiler technology for Cadence’s Palladium hardware emulation platform. Design scalable solutions for large compilation workloads, including model and structural checking. Build, debug, test, and maintain production-quality C/C++ software in Linux/Unix environments, applying multithreading and distributed computing. Collaborate with global engineering teams on design, validation, and issue resolution.

Lead functional verification for Cadence memory controller IP. Develop and enhance UVM-based verification environments, create test plans, validate customer configurations through regression testing, analyze functional and code coverage, support customers using the environment, and ensure designs meet technical and quality requirements.

Develop and verify simulation-efficient analog behavioral models for analog and RF blocks using SystemVerilog. Integrate models with RTL, validate them against analog schematics and design specifications, and create testbenches, scenarios, and assertions. The role also involves low-power architecture, Cadence Virtuoso and ADE workflows, documenting verification results, and collaborating with an engineering team. New graduates are encouraged to apply; DSP, FPGA prototyping, and testbench development experience are beneficial.