Teams at Cadence Design Systems

Lead digital design engineer responsible for designing and integrating SoC IPs, developing microarchitectural specifications, performing lint, CDC, synthesis, and PPA optimization, and supporting verification and physical design teams. The role also involves creating synthesis constraints, debugging design issues, automating repetitive tasks with scripting, and collaborating across engineering teams.

Leads customer-facing digital implementation and signoff initiatives from RTL to GDSII. Responsibilities include synthesis, floorplanning, place and route, timing and power closure, clock tree synthesis, PPA optimization, flow automation, technical presentations, customer support, and collaboration with R&D on Cadence EDA tools and methodologies for advanced-node SoC tape-outs.

Provides pre-sales and post-sales technical support for Cadence digital implementation and signoff tools. Responsibilities include customer presentations, workshops, demonstrations, benchmarks, technical evaluations, methodology consultations, solution implementation, account campaigns, customer support, and collaboration with R&D. Requires expertise in timing signoff, advanced-node static timing analysis, constraints debugging, ASIC implementation flows, scripting, and customer-facing communication. Travel is required up to 20%.