Teams at Cadence Design Systems

The Sr Principal Product Engineer will lead STA product development, bridge customer needs with R&D, create specifications, and enhance tool quality. Key focus on Tempus timing tools and customer engagement.

The Lead Design Engineer at Cadence will manage PCIe Controller designs, support customers with integration, and collaborate with R&D and verification teams.

Lead and execute functional design verification using SystemVerilog and UVM. Develop verification environments, test plans, and drive verification closure for complex designs. Mentor teams and coordinate environment planning; memory IP experience (DDR/HBM/GDDR) is a plus.