Cadence Design Systems

HQ
San Jose
Total Offices: 26
8,216 Total Employees
Year Founded: 1988

Cadence Design Systems Benefits Overview

Compensation + Benefits

Offers 401(K)

Offers life insurance

Offers supplemental life insurance

Offers accidental death & dismemberment insurance

Offers disability insurance

Offers charitable contribution matching

Offers occupational accident insurance

Provides adoption assistance

Provides family medical leave

Provides fertility benefits

Offers childcare benefits

Offers generous parental leave

Offers company equity

Offers performance bonuses

Offers employee stock purchase plan

Offers employee discounts

Offers dental insurance

Offers health insurance

Offers mental health benefits

Offers dependent care

Offers Flexible Spending Account (FSA)

Offers vision insurance

Offers Health Savings Account (HSA)

Company Culture

Provides commuter benefits

Offers travel concierge services

Provides a mobile phone discount

Offers legal assistance

Utilizes a flexible work schedule

Offers a remote work program

Offers diversity-based Employee Resource Groups

Work-Life Balance + Wellbeing

Offers company-sponsored outings

Offers gym membership

Offers an Employee Assistance Program (EAP)

Offers generous PTO

Provides paid holidays

Provides bereavement leave

Offers unpaid extended leave

Offers paid volunteer time

Provides paid sick days

Provides military leave

Career Growth + Development

Provides customized development tracks

Job training & conferences

Provides tuition assistance

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Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
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Paris, Île-de-France, FRA
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
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In-Office
Austin, TX, USA
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Architects and designs processor core logic enhancements in partnership with the Chief Architect. Collaborates with validation and physical design teams to productize solutions, focusing on areas such as load/store, instruction fetch, branch prediction, memory management, and bus protocols. The role may also analyze performance bottlenecks, model improvements, and implement optimization solutions.