Teams at Baya Systems

Own RTL-to-GDS physical implementation for high-performance SoC and chiplet designs, including synthesis, floorplanning, placement and routing, clock tree synthesis, timing and power closure, EM/IR analysis, physical design validation, DRC, LVS, and final signoff. Collaborate with microarchitects on performance, power, and area trade-offs, conduct feasibility studies, and develop physical design methodologies and automation recipes.

As a Hardware Verification Engineer, you will create test plans, write UVM/SystemVerilog code, collaborate with software teams, and conduct failure debug for SoC and chiplet systems.

Lead and grow a team of RTL microarchitects and DV engineers to deliver high-speed interconnect IP from microarchitecture through RTL and tape-out. Drive verification (UVM/OVM, formal, coverage), cross-functional PPA tradeoffs, and engineering processes to ensure first-pass silicon success.