Teams at Axelera AI

Lead ASIC physical design activities from RTL to GDS including synthesis, floorplanning, place-and-route, CTS, timing optimization, extraction, physical verification, EMIR signoff, and IP integration. Drive automation with Python/Tcl/Bash, debug physical-design challenges, and collaborate closely with architecture, RTL, and verification teams to deliver multi-core in-memory compute SoCs.

Perform ASIC physical design tasks from RTL to GDS including synthesis, floorplanning, P&R, extraction, timing analysis, CTS, and physical verification. Integrate IPs (memories, I/Os, processors), use EDA tools (PrimeTime, Fusion, Calibre, Redhawk), write automation scripts (Python/Tcl/Bash), debug issues, and collaborate with architecture, RTL, and verification teams.

Lead and build Axelera's AI Infrastructure Systems division to deliver datacenter-class hardware from accelerator cards and OAM/UBB modules to 1U/2U racks. Own architecture, schematics, PCB/layout review, power/thermal/mechanical design, BMC/firmware, bring-up, validation, qualification, NPI, and ramp with CMs/ODMs. Align roadmaps with silicon, SDK, and product teams, engage customers and partners, set engineering processes, manage budget and vendor relationships, and mitigate technical risks through hands-on leadership.