Jobs at Architect

Own ambiguous, high-priority projects for the founders and leadership team, driving them from planning through completion. Responsibilities span financial planning, budgeting, reporting, purchasing, vendor management, legal coordination, recruiting, onboarding, HR processes, and operational decisions. The role requires building scalable systems, using AI and automation, resolving urgent issues, and improving company operations in a high-trust startup environment.

Lead the end-to-end delivery of advanced AI ASICs, spanning microarchitecture, RTL, verification, physical design, signoff, tapeout, and silicon bring-up. Build AI-native, automated chip-development methodologies, improve PPA and silicon quality, make critical technical and execution decisions, and recruit and lead a world-class silicon engineering organization.

Define the architectural vision for next-generation AI compute silicon and lead decisions across compute, memory, interconnect, and hardware-software co-design. Build architecture-search systems connecting workload analysis, design-space exploration, performance modeling, and PPA feedback. Partner with ASIC and software leaders to develop production silicon while making critical technical tradeoffs. The role requires a proven architect and technical leader with multiple shipped CPUs, GPUs, AI accelerators, or complex SoCs.

Own the microarchitecture and synthesizable RTL design of production memory subsystems for AI ASICs. Design DDR, LPDDR, and HBM controllers, cache hierarchies, memory-side accelerators, scheduling, ECC, QoS, and interfaces. Drive RTL through lint, CDC, synthesis, timing, area, and power closure; collaborate with verification, software, ML, and physical design teams. Support FPGA prototyping and AI-driven design automation using SystemVerilog and Python.

Lead microarchitecture and RTL design for on-chip interconnects and high-speed fabric. Own NoC/router/crossbar architecture, AMBA-compliant interconnects, HSIO bridges (PCIe/CXL/UCIe), peer-to-peer DMA engines, RTL infrastructure, FPGA prototyping, and verification collaboration to achieve low-latency, high-bandwidth, deadlock-free SoC communication and production tapeout readiness.