Altera (altera.com) Benefits Overview

Consult on and optimize Workday Recruiting and Learning processes globally: streamline workflows, increase recruiter efficiency, improve onboarding and learning administration, build dashboards and analytics, identify automation/AI opportunities, and partner with HR, TA, and business leaders to implement scalable Workday solutions and a long-term optimization roadmap.

Lead end-to-end STA and physical-design closure for advanced-node SoC/ASIC programs, drive timing and tapeout readiness, resolve complex timing/PD issues, define closure methodologies, partner with cross-functional teams and foundries, and mentor STA/PD engineers.

Design, implement, and debug FPGA-based prototypes for ASIC validation and prototyping. Develop RTL in Verilog/SystemVerilog, integrate high-speed IPs (PCIe, DDR/LPDDR, Ethernet, CXL, HBM), perform synthesis/place-and-route/timing closure, and create automation scripts. Collaborate with architecture, verification, firmware, and post-silicon teams to resolve functional and performance issues and improve FPGA methodology and bring-up plans.