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The Senior Engineer I - VLSI position involves high-speed design for edge computing applications, working with EDA tools, timing analysis, and synthesis, while collaborating with physical design teams on complex clocking issues. The role requires hands-on experience with deep sub-micron tech nodes and understanding of power management and signal integrity concepts.

The Senior Executive Finance II will manage accounts payable and receivable processes, perform general ledger accounting, oversee payroll, and prepare financial reports. The role involves ensuring compliance with financial regulations, assisting with audits, and identifying process improvements within a global finance shared service center.

The Senior Staff Engineer I will manage the verification of IPs, Blocks, or Subsystems at the SoC level, develop documentation, analyze/debug verification tasks, and create the verification environment and components.

Develop and deliver Interface and Analog IPs, focusing on Hard Analog or PHY blocks design for internal ASIC or external customers. Support multiple customers and ensure success through robust IP development methodology.

As a Senior Technical Solutions Engineer, you'll prepare and present technical solutions to customers, work closely with engineers to optimize product performance, lead technical responses to RFI and RFQ, and build relationships with customer management. Your role involves collaboration with marketing and attendance at relevant trade shows, requiring occasional travel.

The Principal Engineer in Analog Design will focus on designing and simulating high-speed circuits, mentoring junior designers, supporting library generation and validation, and conducting post-layout simulations. The role requires a strong background in analog circuit design, particularly in high-speed interfaces and a proven track record in SoC designs.

The Senior Engineer I - VLSI will deliver standards-compliant IP blocks for OTN/Ethernet/CXL/PCIe FPGAs or ASICs, lead projects, refine development processes, architect verification environments using SystemVerilog and UVM, develop test plans and individual test cases, and mentor junior engineers while tracking bug reports and collaborating with customers.