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The APAC Country Manager is responsible for overseeing all operations in the APAC region, fostering relationships with stakeholders, managing financial performance, ensuring compliance, leading local strategic initiatives, and reporting to corporate management while building and leading a team.
In this role, you will lead customer engagements and manage ASIC product programs from concept through mass production. Responsibilities include planning and budgeting, tracking program performance, customer feedback management, and regular communication with internal teams and executives. You will ensure that products meet customer expectations while overseeing technical and managerial aspects.
The Staff Design Verification Engineer at Alphawave Semi will architect, design, and verify DSPs using high-speed mixed-signal PHYs. Responsibilities include developing scalable testbench components with UVM, overseeing the verification process, collaborating with design teams, and mentoring junior members.
The Staff Engineer II - Analog Layout will lead layout design activities, produce high-quality IPs and work closely with the design team. Responsibilities include area estimation, floor planning, and verification processes, along with mentoring junior engineers and developing scripts.
In this role, you will lead the verification of IP and sub-systems, develop scoreboard mechanisms and monitoring for issue detection, create verification environment components, code tests and assertions, and ensure functional coverage while debugging failures and managing regression testing.
The Physical Design Engineer will work on advanced place and route flow using CAD tools, collaborating with design and verification teams, integrating complex analog IPs, and performing physical verification tasks. Responsibilities include block and chip level floor-planning and developing layout software automation capabilities.
As a Staff Engineer I for RTL Design, you will lead architecture proposals, manage design teams, and ensure delivery on various key projects aligning with ARM architecture and IP integration, while overseeing progress with cross-functional teams.
Responsible for the verification of IP, Block, or Subsystem at SoC Level, including generating documentation, debugging, and developing verification environments. Requires expertise in digital verification methodologies and protocols.
The Senior Staff Engineer I will perform physical design and verification tasks on ASIC projects, managing development flows in advanced process nodes. Responsibilities include floor-planning, timing closure, and coordination of verification activities while mentoring junior team members.
The Staff Engineer I - Physical Design will handle physical design and verification tasks for ASIC development, including floor-planning, timing closure, and IR/EM analysis. The role involves mentoring junior team members and ensuring the integration of different design components. Reporting to the ASIC Design Director, the engineer will work in a hybrid environment managing project-specific workflows.
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