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Join a hardware startup in Silicon Valley as a Silicon PDV Engineering Manager responsible for developing PDV methodology, driving convergence, performing full chip integration, and managing a team of engineers. Must have deep understanding of advanced process nodes, experience in full chip convergence for high-end chip designs, and strong scripting skills in tcl and python.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories, optimize power and performance metrics, and support silicon bring up. Responsibilities involve circuit design, simulation, equivalence checking, PPA analysis, and collaboration with cross-functional teams.

Responsible for internal interconnect architecture specification and performance optimization. Collaborate with Silicon team members and industry consortiums. Develop, assess, and refine architecture to meet power, performance, and timing goals.

Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Responsible for bringing up power intent checking flows, debugging issues, and optimizing for low power. Requires strong communication, interpersonal skills, and scripting abilities in Tcl and Python.

Develop PDV methodology and infrastructure for large SoCs, drive convergence at full chip level, work with internal and external design teams, manage team of engineers for PDV convergence.

As a Sr. ATE test engineer, responsible for test, characterization, and HVM shipment of Silicon. Develop production, qualification, and characterization test programs. In charge of test pattern conversion, hardware bring-up, and first-Si test pattern bring-up. Define test requirements, drive ATE to System level correlation, work on failure analysis, and debug during NPI phase. Require 10-12 years of ATE experience, strong hardware design understanding, hands-on experience with ATE test equipment, team leadership experience, and DfT experience. Bachelor's or Master's Degree in technical subject area.

Seeking a Senior Memory Design Engineer with 8-10 years of experience in custom circuit design, SRAM memories, Register file memories, SRAM compilers, and low power design techniques. Responsibilities include driving the design and development of custom circuits, working with microarchitecture team, conducting PPA analysis, equivalence checking, collaborating with CPU and SoC teams, and interacting with technology and CAD teams.