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The Senior Memory Design Engineer will develop custom SRAM and register file memories to enhance circuit performance while optimizing power. Responsibilities include designing custom circuits, conducting PPA analysis, collaborating with various teams for design implementation, and ensuring high-quality design collateral. A solid background in circuit design and low power techniques is essential.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories. Responsibilities include driving the design and development of custom cells for high performance and low power designs, conducting PPA analysis, equivalence checking, collaborating with various teams, and delivering high-quality design collateral.

The Fabric/Interconnect Architect will design and specify internal interconnect architectures for computing platforms, focusing on both coherent and non-coherent interconnects. They will collaborate with the silicon team on performance, power, and area specifications, ensuring high-level architectural goals are met through detailed design and validation plans.