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Design and implement test strategies for AI ASICs used in wearable devices. Collaborate with design and verification teams, manage third-party implementations, and support yield enhancement. This role requires hands-on experience with SCAN, MBIST, boundary scan, and testing high-speed interfaces.
The ASIC Design Engineer will micro-architect, design, implement, and debug IP designs while collaborating with a diverse team. Key responsibilities include implementing AI-related IPs, developing regression tests, analyzing code coverage, and contributing to documentation.
As an ASIC Verification Engineer at Snap Inc, you will assure quality in ASIC designs, manage verification processes across project lifecycles, and collaborate with global teams to enhance design accuracy and efficiency. Responsibilities include developing test plans, debugging, and improving verification methodologies in a diverse team.
As a SoC Design Engineer at Snap Inc, you will be responsible for the design and implementation of SoC subsystems, writing architectural specifications, integrating subsystems, and ensuring design quality through various flows. You will also collaborate with teams to improve performance, power, and area metrics.
The IC Physical Design Engineer at Snap will contribute to artificial intelligence ASIC design for wearable devices, focusing on physical implementation from netlist to GDSII. Responsibilities include ensuring designs meet timing and power targets, leading DRC/LVS analysis, and improving CAD methodology while collaborating with international teams.
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