The Role
Develop and maintain UVM-based constrained-random verification environments for RTL and full-chip designs. Create coverage models, verification plans, directed and random tests, and regression infrastructure. Debug simulation failures and collaborate with designers on RTL fixes. Support scripting, CI/CD, design and specification reviews, and silicon bringup while tracking verification sign-off metrics.
Summary Generated by Built In
Key Responsibilities
• Develop and maintain constrained-random UVM testbenches for RTL blocks and fullchip
verification.
• Write functional coverage models and coverage closure plans to drive verification
completeness.
• Author and execute directed and random test scenarios targeting corner cases and
protocol compliance.
• Debug simulation failures, identify root causes in RTL, and collaborate with designers on
fixes.
• Develop verification plans (VPlans) based on micro-architecture specifications and track
sign-off metrics.
• Contribute to regression infrastructure, CI/CD pipelines, and EDA tool flow scripting.
• Participate in design reviews, spec reviews, and silicon bringup activities.
Required Qualifications
• B.Sc. / M.Sc. / Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of hands-on VLSI verification experience in an industry setting.
• Strong proficiency in SystemVerilog and UVM methodology (environments, agents,
sequences, scoreboards). Strong proficiency in Specman language & methodology
• Experience with industry simulation tools: VCS, Xcelium, ModelSim/Questa.
• Solid understanding of digital design fundamentals, RTL coding, and microarchitecture
concepts.
• Familiarity with assertion-based verification (SVA) and coverage-driven verification.
• Scripting skills in Python, Perl, or Tcl for automation and flow development.
Skills Required
- B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of hands-on industry VLSI verification experience
- Strong proficiency in SystemVerilog and UVM methodology, including environments, agents, sequences, and scoreboards
- Strong proficiency in Specman language and methodology
- Experience with VCS, Xcelium, and ModelSim/Questa simulation tools
- Understanding of digital design fundamentals, RTL coding, and microarchitecture concepts
- Familiarity with assertion-based verification using SVA and coverage-driven verification
- Scripting skills in Python, Perl, or Tcl
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The Company
What We Do
HCCM Consulting is a Lisbon-based technology consultancy that has provided software development and professional services since 1995. The company specializes in creating custom CRM software, business automation solutions, website development, and mobile applications. They serve diverse sectors including banking, insurance, energy, retail, and telecommunications, leveraging their expertise in enterprise applications, nearshoring, and the implementation of low-code technologies.
