Synthesis or Formal Verification Developer at YosysHQ

Posted 2 Days Ago
Be an Early Applicant
Hiring Remotely in Vienna, AUT
In-Office or Remote
6K-6K
Mid level
Software • Business Intelligence • Semiconductor • Automation
The Role
Work on open-source EDA tools focusing on synthesis or formal verification. Contribute in C++, Rust, and Python to implement/extend model checking, verification algorithms, or synthesis flows. Require RTL design familiarity, ability to navigate large existing codebases, and work independently as a remote contractor for an Austrian company with CET meeting hours.
Summary Generated by Built In
You might know YosysHQ from our many Open Source EDA Projects. We are the maintainers of Yosys and the accompanying Open Source EDA ecosystem. Our team is pushing the boundaries of EDA in interesting and unexpected ways, and making these tools and methodologies available for professionals, hobbyists and academics alike.
We offer off-the-shelf software packages that seamlessly integrate our tools in industry design environments and provide support and training for users of our software packages. We also offer custom development of individual features and entire flows based on our software components, and support and training for developers working on custom projects based on our Open Source work.
We are around 12 people, with two main focus areas: synthesis and formal verification. If you can contribute to either of these areas, we welcome your application.
Tasks
For the formal verification area:
* Our tools use C++, Rust, and Python. You should already be comfortable with either C++ or Rust, and willing to learn the others.
* Ideally, you would be familiar with the implementation side of hardware model checking.
* Alternatively, we think you would be able to succeed if you have a background in the general area of verification or formal methods (such as SAT/SMT solving, automated/interactive theorem proving, programming language theory or automata theory), and have had a little bit of contact with RTL hardware design.
For the synthesis area:
* You should be comfortable with C++.
* You should have some experience with RTL hardware design (ideally for ASIC).
* Any of the following experiences would likely transfer to this job:
* Building software for engineering or science applications
* Implementing a practical application based on an algorithm in the scientific literature
* Working on a compiler
As we are a small and busy team, we have limited resources for training. To succeed in this role you will need to have some experience in getting familiar with a large-ish pre-existing project. You’ll need to be comfortable taking responsibility for assigned tasks, working through them independently, and addressing challenges without needing extensive supervision.
Requirements
Important Notes
This is a flexible remote role which could be part time (1-5 days per week).
You would be working as an independent contractor/freelancer for an Austrian company, from wherever you are. Our team meetings usually take place between 3pm and 6pm Vienna time (CET/CEST), otherwise you can choose to work whenever you want.
YosysHQ has a flat pay hierarchy, where everyone earns the same rate: currently 6000€/month for full time contract work. As such, the only parameter that can be negotiated is the days per week.
As YosysHQ works with US government contractors, you must not be living in a country subject to sanctions or export restrictions, or banned from performing work for the US government for other reasons.
How to Apply:
Even if your background doesn’t perfectly align with these areas, we’re always interested in hearing from passionate and skilled individuals. If you’re intrigued by the work we do, please send us your CV and a brief cover letter detailing how your past experience translates to the work we do.
We’re especially excited to hear from candidates who have interacted with or contributed to our open-source tools—though this is not a requirement. Show us your potential, and let’s explore how you can make an impact!

Skills Required

  • Comfortable with either C++ or Rust and willing to learn other languages
  • Comfortable with C++ (required for synthesis-area work)
  • Some experience with RTL hardware design (ideally for ASIC)
  • Familiarity with implementation-side hardware model checking
  • Background in verification or formal methods (SAT/SMT, theorem proving, PL theory, automata) with some RTL exposure
  • Experience getting familiar with large pre-existing projects and working independently with limited supervision
  • Ability to work as an independent contractor/freelancer for an Austrian company and attend team meetings ~3–6pm CET
  • Not residing in countries subject to sanctions or export restrictions or otherwise banned from performing work for the US government
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The Company
12 Employees

What We Do

YosysHQ is the organization that maintains Yosys and related open-source Electronic Design Automation (EDA) projects. They provide commercial software packages, including the Tabby CAD Suite, as well as custom development, support, and training for professional users. The company focuses on pushing the boundaries of EDA, offering tools for RTL synthesis and formal verification to a diverse audience of professionals, hobbyists, and academics.

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