Staff Systems Engineer, AI/ML

Posted 2 Days Ago
3 Locations
In-Office
106K-205K Annually
Mid level
Semiconductor • Manufacturing
The Role
Lead workload-driven AI/ML systems architecture across hardware and software. Own workload characterization, analytical performance modeling, KPI definition, and hardware performance analysis to guide SoC, memory, and HW/SW co-design decisions. Evaluate compute, memory, latency, and software bottlenecks; collaborate with CPU, compiler, runtime, and ML framework teams; present recommendations to leadership; and mentor junior engineers. The role requires expertise in processor and memory architecture, edge AI acceleration, performance modeling, and cross-functional technical leadership.
Summary Generated by Built In

Title: Staff System Engineers Engineer, AI/ML

About GlobalFoundries: 

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. 

Summary of Role:

We are looking for a seasoned Staff AI/ML Systems Engineer to lead workload-driven architecture strategy across hardware and software boundaries. You will define how we study, model, and optimize AI/ML workloads for current and next-generation products, drive alignment across HW and SW engineering organizations, and serve as a technical authority on performance and architecture tradeoffs. This is a senior individual contributor role with significant cross-functional scope and organizational influence.

Essential Responsibilities:

  • You will own the end-to-end process of workload characterization and hardware performance analysis for AI/ML systems — from selecting the right representative workloads and defining measurement methodology, to building analytical models that project system-level KPIs against candidate architectures. Your findings will directly inform SoC architecture decisions, memory subsystem design, and HW/SW co-optimization strategy.
  • You will lead architectural discussions with hardware teams (CPU, SoC, memory, interconnect) and software teams (compilers, runtimes, ML frameworks), serving as the connective tissue between workload reality and design decisions. You will identify where the critical bottlenecks lie — whether in compute throughput, DRAM bandwidth, on-chip memory capacity, data movement latency, or software overhead — and build the case for specific architectural changes or optimization investments.
  • A core part of this role is defining the performance KPI framework for AI/ML workloads across the product portfolio: what metrics matter, how to measure them accurately, how to estimate them pre-silicon, and how to use them to make architectural bets. You will set the standard for how the team does this work and mentor more junior engineers in applying it.
  • You will regularly present findings and recommendations to senior engineering leadership and product stakeholders. Your communication must bridge deep technical content and strategic implication — you should be as comfortable writing a one-page architectural recommendation as a detailed technical memo.

Other Responsibilities: 

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. 

Required Qualifications:

  • A BS or MS (MS preferred) in Electrical Engineering, Computer Engineering, Computer Science, or equivalent, with 4+ years of industry experience in systems engineering, hardware architecture, ML systems, or performance engineering, with a track record of technical leadership.
  • Exceptional mathematical reasoning is a core requirement at this level. You should be able to derive and defend analytical performance models from first principles, reason rigorously about the numerical behavior of quantized and sparse models, construct bandwidth-latency tradeoff curves across memory hierarchy levels, and identify when an approximation in a model is safe versus misleading. You will also be expected to evaluate the mathematical soundness of others' models and call out gaps in cross-functional reviews.
  • Deep expertise in CPU and SoC architecture is expected — you should be fluent in how modern processors handle memory hierarchies, out-of-order execution, vector/SIMD pipelines, and power management, and understand how these interact with AI/ML workloads. You should have strong command of memory bandwidth constraints at the system level (DDR/LPDDR bandwidth, channel configuration, utilization efficiency) and know how to reason quantitatively about when workloads are memory-bound vs. compute-bound.
  • You have built and validated analytical performance models (roofline, bandwidth-latency, first-principles throughput models) and know their limits. You have experience with AI/ML acceleration on edge devices — NPUs, dedicated inference accelerators, DSP-based pipelines — and understand the HW/SW co-design challenges involved. Experience with model quantization, sparsity, or other efficiency techniques and their interaction with hardware capabilities is a strong plus.
  • Familiarity with AI compiler infrastructure is preferred and increasingly important in this role. Experience with MLIR-based toolchains, IREE, TVM, or equivalent compilation and lowering pipelines — understanding how high-level graph representations are transformed, tiled, scheduled, and lowered to hardware — will meaningfully improve your ability to engage with software teams and identify where compiler strategy and hardware architecture must be co-designed. Prior work contributing to or evaluating such toolchains is a significant differentiator.
  • You are an effective cross-functional collaborator who can drive technical consensus without direct authority. You write clearly, present persuasively, and can calibrate your level of technical depth for different audiences.

What Sets Strong Candidates Apart

Prior experience defining or co-defining SoC architecture requirements from workload analysis, contributions to MLIR/IREE or similar compiler infrastructure in a performance or backend capacity, contributions to internal or external publications or technical standards, and experience mentoring and growing junior systems engineers. Knowledge of RISC-V architecture and Vector/Matrix extensions is a strong plus.

Other Requirements:

  • Language Fluency - English (Written & Verbal)
  • Travel - Up to 10% of the time

This is a 100% in-office role (Dallas/Austin/San Jose)

Expected Salary Range

$106,000.00 - $205,000.00

The exact Salary will be determined based on qualifications, experience and location.

If you need a reasonable accommodation for any part of the employment process, please contact us by email at [email protected] and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address. 

 

An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations. 

 

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory. 

 

All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law 

Skills Required

  • BS or MS degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent; MS preferred
  • 4+ years of industry experience in systems engineering, hardware architecture, ML systems, or performance engineering
  • Track record of technical leadership
  • Exceptional mathematical reasoning, including analytical performance modeling and quantitative workload analysis
  • Deep expertise in CPU and SoC architecture, including memory hierarchies, out-of-order execution, vector/SIMD pipelines, and power management
  • Strong understanding of system-level memory bandwidth constraints, including DDR/LPDDR bandwidth, channel configuration, and utilization efficiency
  • Experience building and validating analytical performance models such as roofline, bandwidth-latency, and first-principles throughput models
  • Experience with AI/ML acceleration on edge devices, including NPUs, inference accelerators, or DSP-based pipelines
  • Experience with model quantization, sparsity, or other AI/ML efficiency techniques
  • Familiarity with AI compiler infrastructure such as MLIR, IREE, TVM, or equivalent compilation and lowering pipelines
  • Effective cross-functional collaboration, clear technical writing, persuasive presentation, and consensus building without direct authority
  • English language fluency, written and verbal
  • Knowledge of RISC-V architecture and Vector/Matrix extensions
  • Experience defining or co-defining SoC architecture requirements from workload analysis
  • Contributions to MLIR, IREE, or similar compiler infrastructure
  • Contributions to internal or external publications or technical standards
  • Experience mentoring and developing junior systems engineers

GlobalFoundries Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about GlobalFoundries and has not been reviewed or approved by GlobalFoundries.

  • Healthcare Strength Comprehensive medical, dental, vision, life, disability, and mental health support is presented as a meaningful part of the package. Wellness programs and an Employee Assistance Program add to the sense of broad health coverage.
  • Retirement Support A 401(k) with matching from day one and access to an employee stock purchase program are positioned as notable financial benefits. Retirement provisions are repeatedly framed as a strong counterweight to other compensation concerns.
  • Leave & Time Off Breadth Time-off provisions are described as generous, including high annual vacation accrual, dedicated sick time, and additional personal days. Extended paid parental leave frameworks are also outlined as a substantial leave benefit.

GlobalFoundries Insights

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The Company
HQ: Malta, NY
12,676 Employees
Year Founded: 2009

What We Do

GlobalFoundries (GF) is one of the world’s leading semiconductor manufacturers. GF is redefining innovation and semiconductor manufacturing by developing and delivering feature-rich process technology solutions that provide leadership performance in pervasive high growth markets. GF offers a unique mix of design, development, and fabrication services. With a talented and diverse workforce and an at-scale manufacturing footprint spanning the U.S., Europe and Asia, GF is a trusted technology source to its worldwide customers. For more information, visit www.gf.com. GlobalFoundries is an Equal Employment Opportunity/Affirmative Action (EEO/AA) employer Minorities/Female/Disabled/Veteran (M/F/D/V).#CB

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