Staff Software Engineer, LLM Inference Platform

About Zenlayer

Zenlayer is the first massively distributed edge cloud provider, operating 290+ Points of Presence across 70+ countries. With accolades including PTC “Best Networking Innovation”, “Outstanding Cloud, Data Center, or Interconnection Company”, and Inc. 5000, we enable businesses to deploy and run applications at the edge, thus reducing network latency to the end user. Zenlayer focuses on improving connections worldwide, all while nurturing a unique company culture that values service, growth, and trust. As a “Zenplayer”, you’ll be joining a community of success-driven team players that share the dream of powering a better-connected world.

About the Role: 

As the technical lead for inference performance, you will own end-to-end responsibility for the platform's Token Performance. For models ranging from hundreds of billions to trillions of parameters (including MoE), you will continuously reduce cost per million tokens and increase per-GPU Goodput while meeting TTFT/TPOT SLOs, and prove the gain from every optimization with reproducible data. 

What You Will Work On 

1. End-to-End Performance Attribution and Benchmarking 

• Establish a unified Token Performance metrics framework (TTFT, TPOT, Goodput, GPU utilization, per-token cost), and build load-testing benchmarks that reflect real production traffic (high concurrency, long context, multi-turn Agent workloads) 

• Perform bottleneck attribution for models such as DeepSeek, Kimi, GLM, Qwen, and MiniMax across compute, memory bandwidth, communication, scheduling, and queuing, and let the data determine which layer is the dominant constraint 

2. Kernel-Level Inference Engine Optimization 

• Dive deep into the source code of vLLM / SGLang / TensorRT-LLM, customizing and contributing upstream on critical paths such as the scheduler, Continuous Batching, Chunked Prefill, CUDA Graph, and KV block management 

• Clearly define the responsibility boundary between the inference engine and orchestration layers such as Dynamo / llm-d, and reduce tail latency through request routing and load balancing 

3. PD Disaggregation and KV Cache Transfer 

• Lead the core design of Prefill-Decode disaggregation: the KV transfer path (NIXL/RDMA/UCX), transfer-compute overlap, and phase-aware autoscaling 

• Define the failure domains and recovery semantics of cross-instance KV transfer, and answer the key question: under which workloads does PD disaggregation deliver gains, and under which does it make things slower 

4. MoE Parallelism and Wide-EP 

• Design hybrid TP/PP/DP/EP parallelism strategies and quantify the trade-offs between EP and TP 

• Tackle expert load imbalance and All-to-All communication overhead, and drive Wide-EP into production 

5. Kernels and Quantization 

• Write and tune critical CUDA (and ROCm/HIP) operators: memory access optimization, kernel fusion, and Attention / MoE / communication-related kernels 

• Build a closed-loop "quantization – accuracy – throughput" evaluation: the real-world gains and accuracy regressions of FP8/FP4/INT4/AWQ/GPTQ across different engines and hardware 
  

Requirements 

• First-principles understanding of Transformer inference: the compute vs. memory-bound nature of Prefill and Decode, the KV Cache memory model, the differences among MHA/GQA/MLA, and how MoE routing constrains parallelism 

• Source-level, in-depth experience with at least one mainstream inference engine, with real cases of identifying and fixing bottlenecks in scheduling, kernel selection, or KV management 

• CUDA kernel tuning skills (Nsight profiling, memory optimization, fusion, CUDA Graph) with hands-on practical experience 

• Bachelor’s degree in Computer Science, Electrical/Computer Engineering, or related field (HPC systems, ML Systems). 

• Minimum 6 years in systems/Performance Engineering, with at least 2-3 years directly on LLM or GPU performance work 

Preferred, but not required:  

• Experience with Merged PRs in vLLM 

• Experience operating at cluster sale (hundreds to thousands of GPUs)