The Role
Lead physical design and implementation for complex SoC and SerDes/interconnect designs from RTL through GDSII tapeout. Responsibilities include floorplanning, power and clock planning, place-and-route, PPA optimization, timing, power, noise, EM/IR-drop analysis, physical verification, signoff, IP integration, flow automation, and methodology development.
Summary Generated by Built In
Credo is seeking a Staff Physical Design Engineer to join our Digital R&D team. In this role, you will lead all aspects of physical design and implementation for SoC designs, collaborating closely with frontend and PD/Integration teams across our China and Taiwan offices to drive successful tape outs.
Why Credo
Qualifications
Basic Qualifications
Responsibilities
Benefits
Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.
Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.
Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [email protected].
Why Credo
- Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
- People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
- Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.
Qualifications
Basic Qualifications
- BS/MS in EE/CS with a minimum of 8+ years of recent hands-on experience as a Physical Design Engineer.
- Familiar with hierarchical physical design strategies, methodologies.
- Experience with 5nm and lower technology nodes.
- Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure.
- Strong proficiency with EDA tools such as Cadence, Innovus, and Synopsys Fusion Compiler.
- Solid knowledge on static timing analysis (PrimeTime/Tempus), EM/IR-Drop/crosstalk analysis (PTSI/Voltus/Redhawk), extraction (Quantus/StarRC).
- Familiar with DRC, Antenna, LVS, ERC tools like Calibre.
Responsibilities
- Lead and drive Top-Level/IP/block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems.
- Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, power planning/analysis, place-and-route, physical verification and sign-off.
- Perform static timing analysis, power and noise analysis and physical verification.
- Deliver IP hardening/integration and verification.
- Work closely with frontend and integration team to ensure successful tape outs.
Benefits
Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.
Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.
Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [email protected].
Skills Required
- BS or MS degree in Electrical Engineering or Computer Science
- At least 8 years of recent hands-on physical design engineering experience
- Experience with hierarchical physical design strategies and methodologies
- Experience with 5nm and smaller technology nodes
- Ability to independently handle chip-level place-and-route and tape out complex SoC chips
- Proficiency with Cadence Innovus and Synopsys Fusion Compiler
- Knowledge of static timing analysis using PrimeTime or Tempus
- Knowledge of EM, IR-drop, and crosstalk analysis using PTSI, Voltus, or RedHawk
- Experience with extraction tools such as Quantus or StarRC
- Familiarity with Calibre DRC, antenna, LVS, and ERC tools
Am I A Good Fit?
Get Personalized Job Insights.
Our AI-powered fit analysis compares your resume with a job listing so you know if your skills & experience align.
Success! Refresh the page to see how your skills align with this role.
The Company
What We Do
Credo is a semiconductor and connectivity technology company developing fast, reliable, energy-efficient solutions for AI-driven applications, cloud computing, and hyperscale networks. Its portfolio is built on SerDes intellectual property, advanced integrated-circuit design, and system-level engineering, supporting data rates up to 1.6T. The company pioneered Active Electrical Cables and provides high-speed interconnect products and IP that reduce bandwidth bottlenecks across modern data-center infrastructure.
.jpeg)
