As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product.
Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
Responsibilities- Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications.
- Design and implement simulation environments and testbenches to validate FPGA functionality and performance.
- Create and run functional and directed/random test scenarios to ensure comprehensive design coverage.
- Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage.
- Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle.
- Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality.
- Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.
- Must have 7-14 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans – at block, sub-chip and chip levels.
- Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools.
- Exposure to UVM (or similar) verification methodologies is required.
- Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred.
- Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred.
- Structured and thorough with analytical and troubleshooting skills.
- Good written and oral communication skills are required.
- Flexible, innovative, self-driven and willing to take initiatives.
- Highly motivated team player with exceptional leadership capability.
Skills Required
- 7–14 years of experience developing SystemVerilog UVM-based test environments and implementing verification plans at block, sub-chip, and chip levels
- Strong HVL coding skills for verification
- Hands-on experience with at least one industry-standard verification simulator, such as VCS, NC, or MTI
- Experience with waveform-based debugging tools
- Exposure to UVM or similar verification methodologies
- Working knowledge of Ethernet, PCIe, I2C, and SPI technologies
- Structured, thorough analytical, and troubleshooting skills
- Good written and oral communication skills
- Flexible, innovative, self-driven, proactive, and willing to take initiative
- Highly motivated team player with leadership capability
- Familiarity with Verilog and Perl
- Working knowledge of RTL design
- Knowledge of telecom protocols
Nokia Compensation & Benefits Highlights
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Equity Value & Accessibility — Equity programs include a global employee share purchase plan with company matching and multi‑year share awards. These mechanisms broaden participation and tie rewards to long‑term outcomes.
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Healthcare Strength — Health coverage includes major medical plans with supplementary options such as vision, legal services, and care navigation. The range of offerings indicates comprehensive support for medical needs.
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Parental & Family Support — A global policy grants paid leave for new parents regardless of gender and provides structured return‑to‑work support. Company‑paid life insurance further strengthens family protection across regions.
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