Staff Engineer, DFT Engineering

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

We are seeking a SoC DFT Lead who will be responsible for defining the SoC DFT architecture, collaborating with customers and internal teams, and supervising the end-to-end SoC DFT process, from architecture definition to silicon bring-up.

Responsibilities:

• Lead the DFT team responsible for delivering comprehensive DFT solutions for complex SoCs.
• Take end-to-end ownership of the DFT lifecycle – from architecture definition to silicon bring-up and production ramp.
• Collaborate cross-functionally with architecture, design, and physical design teams to ensure optimal testability integration.
• Define and track DFT milestones, quality metrics, and progress, ensuring alignment with program schedules and quality standards.
• Represent DFT in program and customer meetings, communicating status, risks, and mitigation plans.
• Architect and guide the implementation of DFT features, including Scan chain insertion and optimization, Test compression techniques, LBIST/MBIST (including repair logic), Boundary scan structures
• Lead efforts in performing DFT rule checks (DFT DRC) at RTL and netlist levels to ensure compliance with internal and industry standards.
• Use industry-standard EDA tools (e.g., Cadence, Siemens/Tessent) for DFT Design, DRC, Pattern Generation and work with EDA/Internal CAD team for tool/flow improvements
• Drive DFT pattern generation and validation, including gate-level simulations with and without SDF.
• Partner with the verification team to define and execute DFT verification plans.
• Collaborate with physical design and STA teams to implement DFT constraints and strategies for synthesis and timing closure.
• Analyze silicon test data, debug test failures, and work with the test engineering team to resolve bring-up and production issues.
• Provide technical leadership, mentorship, and career development for DFT engineers on the team.

Qualifications and Experience:

• Proven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up.
• Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs.
• Strong team management and leadership experience with a track record of mentoring and growing engineering talent.
• Bachelor's or Master’s degree in Electrical/Electronics Engineering or a closely related field.
• 7+ years of hands-on experience in DFT methodologies and industry-standard test techniques.
• Deep knowledge and hands-on experience with:

Logic BIST (LBIST)

Automatic Test Pattern Generation (ATPG)

DFT Rule Checks (DFT DRC)

Scan chain compression and stitching

Low-power DFT techniques and constraints

Memory BIST (MBIST) including repair mechanisms

Boundary Scan (IEEE 1149.1)

Analog DFT strategies

JTAG architecture and TAP integration

DFT-specific STA constraints

• Proficient in using industry-standard DFT EDA tools, including cadence, Siemens.
• Strong scripting and automation skills using Perl, Tcl, and/or Python.
• Solid understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow.
• Excellent problem-solving skills, with the ability to troubleshoot and resolve complex DFT issues efficiently.
• Strong communication and interpersonal skills, capable of working effectively in cross-functional and team-oriented environments.

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