STA Engineer

Reposted One Month Ago
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Bengaluru, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Information Technology • Professional Services • Consulting
The Role
Perform synthesis and static timing analysis (STA) for complex SoCs, develop timing and I/O constraints for multi-clock/multi-voltage designs, perform post-layout timing closure and ECOs, run STA signoff, use EDA tools and scripting, and apply formal verification with DFT constraints across advanced process nodes.
Summary Generated by Built In
Company Description

client of FiniteHR

Job Description

• B. Tech. / M. Tech. with 5-8 years of experience in Synthesis, STA

• Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains

• Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff

• Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...)

• Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nm

• Good knowledge of EDA tools from RC, DC, PT, PTSI

• Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints 

• Good knowledge of VLSI process and device characteristics

• Good understanding of deep submicron parasitic effects, crosstalk effects etc.

• TCL, perl scripting

Qualifications

B.Tech. /M.Tech.

5-8 years experience in Synthesis,STA

TCL,Perl Scripting

Additional Information

All your information will be kept confidential according to EEO guidelines.

Skills Required

  • B.Tech. or M.Tech.
  • 5-8 years experience in synthesis and STA
  • Expertise in synthesis of complex SoCs and writing timing constraints for multi-clock, multi-voltage designs
  • Post-layout timing closure experience including timing ECOs and STA signoff for multiple tape-outs
  • I/O constraints development for industry protocols (DDR1/2/3, SDR, LPDDR, Flash, SPI, Ethernet, USBHS, USBFS, JTAG, Display)
  • Hands-on experience with 28nm, 20nm, 14nm, 10nm process nodes
  • Good knowledge of EDA tools (RC, DC, PT, PTSI)
  • Experience in formal verification (RTL-to-netlist, netlist-to-netlist) with DFT constraints
  • Good knowledge of VLSI process and device characteristics
  • Understanding of deep submicron parasitic and crosstalk effects
  • TCL and Perl scripting skills
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The Company

What We Do

FiniteHR is a Human Capital Management organization, has been in business since 2014 in Hyderabad, serving IT and non IT clients in Domestic and International markets. They are a team of dedicated professionals with expertise in recruiting professionals and specialized experts across North America, Asia, Middle East and Europe, acting as an ideal outsourcing partner for recruitment and staffing services.

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