Sr. Staff Design Engineer

Posted Yesterday
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San Jose, CA, USA
In-Office
Senior level
Semiconductor • Manufacturing
The Role
Designs and verifies complex FPGA and SoC systems from concept through board-level validation. Develops and optimizes DDR memory controller soft IP, integrates hardened PHYs and peripheral IP, performs timing analysis and constraint writing, evaluates RISC-V systems, and supports hardware validation, interoperability testing, customer issue resolution, and third-party deliverable quality reviews. Leads technical coordination with software, applications, customers, and other stakeholders.
Summary Generated by Built In
Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

Duties:

 

Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.


This role involves:

  • Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
  • Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
  • Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
  • Analyzing hardware capabilities and contributing to customer solution strategies.
  • Architecting Soft IPs with detailed technical specifications and coordinating development efforts.
  • Collaborating cross-functionally with software and applications teams to communicate requirements, resolve issues, and drive enhancements.

Specific duties include:

  • Architect and develop DDR Memory Controller soft IPs
  • Optimize soft IPs to achieve better performance (latency, size, frequency)
  • FPGA design and implementation using software primitives
  • Integration with third-party hardened PHYs
  • Team leadership and stakeholder management
  • Static Timing Analysis (STA) and constraint writing
  • RISC-V based system design and evaluation
  • Customer support and issue resolution
  • Quality review of third-party deliverables
  • Test development to validate implementation and ensure high quality
     

Minimum Requirements:

  • Bachelor’s degree in Electronics Engineering, Applied Physics or related field
  • 8 years of experience as Design Engineer or related field

Prior experience to include:


  • FPGA and SoC ASIC development.
  • IP for FPGA and ASIC products
  • FPGA RTL design, logic verification, debug and timing closure
  • DDR protocols (e.g.: DDR3, DDR4, LPDDR4, DDR5)
  • High-speed interface subsystems
  • High-speed protocols (PCIe, Ethernet, and MIPI)
  • Peripheral IPs (UART, SPI, I2C, and I3C)
  • Hardware validation and hardware interoperability testing

Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

0.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

Skills Required

  • Bachelor's degree in Electronics Engineering, Applied Physics, or a related field
  • Eight years of experience as a Design Engineer or in a related field
  • Experience with FPGA and SoC ASIC development
  • Experience developing IP for FPGA and ASIC products
  • Experience with FPGA RTL design, logic verification, debugging, and timing closure
  • Experience with DDR protocols, including DDR3, DDR4, LPDDR4, or DDR5
  • Experience with high-speed interface subsystems
  • Experience with PCIe, Ethernet, and MIPI protocols
  • Experience with UART, SPI, I2C, and I3C peripheral IPs
  • Experience with hardware validation and hardware interoperability testing
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The Company
HQ: Hillsboro, OR
975 Employees
Year Founded: 1983

What We Do

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world. Lattice was founded in 1983 and is headquartered in Hillsboro, Oregon with major operations in San Jose, California, Shanghai, China, and Manila, Philippines.

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