Sr. Principal SW Engineer, 3DIC P&R & AI-driven EDA Automation

Reposted 2 Months Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
154K-286K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Design and build scalable EDA flows and AI/LLM-driven automation for 3DIC, interposer, and RDL systems. Implement flow-generation, debugging assistants, root-cause analysis, and platform integration using C++, Tcl, Python, and Java. Collaborate with engineering teams to validate flows, automate constraint-driven designs, and address large-scale, high bump-count and multi-region routing challenges to deliver production-quality solutions.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

  • Product Engineer for Integrity 3D-IC.
  • Developing interfaces and integrating various Cadence tools and engines into the Integrity 3D-IC platform.
  • Working closely with R&D group to develop, integrate and enhance 3D-IC solutions, including 3D-IC system planning, implementation, and analysis/verification, and Agentic AI applications.
  • Collaborating with the field teams in customer engagement and providing technical support and guidance.
  • Communicating and coordinating with multiple R&D groups and field teams to enable 3D-IC solutions to customers.

Position Requirements

  • BS degree with 10+ years or MS degree and 5+ years of engineering work experience in the semiconductor industry.
  • Experience in physical implementation, place-and-route, and signoff tools. Familiar with Cadence digital flows and advanced packaging design with Allegro Package Designer.
  • Knowledge and experience in 3D-IC system planning, implementation, analysis, and signoff flows is a plus
  • Hands-on experience in scripting languages, such as TCL, Perl, YAML, and Python.
  • Good trouble-shooting and technical documentation skills.
  • A self-motivated, proactive leaner and team player, with excellent communication skills and a customer-oriented attitude.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Build scalable EDA flows using C++, Tcl, Python, and Java
  • Strong background in EDA data structures and algorithms
  • Hands-on experience with Tcl, Python, and C++ automation in EDA tools
  • Experience with DB-driven design flows such as Innovus or similar implementation platforms
  • Understanding of 3DIC, interposer, packaging routing, and RDL design flows
  • Knowledge of constraint-driven design including timing, signal integrity, and DRC
  • Experience handling large-scale design problems, including high bump-count designs and multi-region routing
  • Bachelor's or Master's degree in Computer Science, Electrical Engineering, Computer Engineering, or related field
  • Relevant industry experience developing EDA software, design automation flows, AI/LLM-enabled engineering tools, or advanced packaging design solutions
  • Experience with 3DIC, 3.5D, or 2.5D designs
  • Familiarity with EMIR and thermal considerations in advanced packaging environments
  • Experience with LLM or AI systems, including agent frameworks and prompt-to-script automation
  • Knowledge of multi-tool integration and end-to-end flow automation
  • Ability to translate complex EDA workflows into scalable, user-friendly automation solutions

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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