Integrate and verify IP blocks in SoC, and support physical implementation.
Define SoC level specifications, architecture and operation scenario.
Understand standard interface specification (e.g., PCIe) and chip operation scenario to configure IP blocks to be integrated into SoC.
Performance analysis in chip top level (bus, memory bandwidth) simulation and FPGA prototyping.
Master's degree in Electrical Engineering, Computer Science or equivalent practical experience.
2+ years of industry experience in chip design, specializing in SoC integration and design automation
Experience in RTL design and logic synthesis, verification, timing closure
Experience in high-speed connectivity IP (e.g., PCIe, USB, MIPI, etc) is a plus - Experience in video codec (decoder, encoder) is a plus
Experience in interconnect, memory subsystem is a plus
Top Skills
What We Do
FuriosaAI designs and develops data center accelerators for the most advanced AI models and applications.
Our mission is to make AI computing sustainable so everyone on Earth has access to powerful AI.
Our Background
Three misfit engineers with each from HW, SW and algorithm fields who had previously worked for AMD, Qualcomm and Samsung got together and founded FuriosaAI in 2017 to build the world’s best AI chips.
The company has raised more than $100 million, with investments from DSC Investment, Korea Development Bank, and Naver, the largest internet provider in Korea. We have partnered on our first two products with a wide range of industry leaders including TSMC, ASUS, SK Hynix, GUC, and Samsung. FuriosaAI now has over 140 employees across Seoul, Silicon Valley, and Europe.
Our Approach
We are building full stack solutions to offer the most optimal combination of programmability, efficiency, and ease of use. We achieve this through a “first principles” approach to engineering: We start with the core problem, which is how to accelerate.
