Define SI/PI requirements based on IP and system-level specifications.
Perform SI/PI simulations at electromagnetic (EM), circuit, and system levels.
Develop SI/PI methodologies for advanced packaging technologies such as chiplet, 3D-IC, D2D (die-to-die), and C2C (chip-to-chip) interfaces.
Cover SI/PI analysis and optimization at the full system level, including on-chip, package, and PCB domains.
Provide design guidance on stack-up, interconnect routing, PDN architecture, decoupling strategy, and component selection.
Collaborate with silicon, package, and board teams to ensure accurate measurement-simulation correlation and system-level robustness.
Support debug and bring-up efforts in the lab when needed.
Work with internal teams and partners to co-optimize SI/PI solutions.
BS or MS in Electrical Engineering, Physics, or a related field.
8+ years of experience in component- and system-level SI/PI analysis.
Solid understanding of SI/PI fundamentals and methodologies.
Hands-on experience with lab instruments such as VNA, TDR, and real-time oscilloscopes.
Proficient in EDA tools such as SIwave, HFSS, ADS, HSPICE, Allegro, RedHwak-SC, SC-ET, or RedHawk-3DIC.
PhD in Electrical Engineering, Physics, or a related field with 5+ years of relevant industry experience.
Candidates with one or more of the following experiences will be given strong consideration:
SI/PI analysis and optimization for high-speed digital systems and standard interfaces (e.g., PCIe, DDR, Ethernet)
Model and analyze complex 3D structures using EM simulation tools
On-chip Backend sign-off (Static/Dynamic IR, EM)
On-/Off-chip PDN modeling and budgeting
On-chip glitch/jitter/DVD analysis and sign-off methodology, including cross-talk, TSV uncertainty, and multi-corner/process derating
Early-stage reference clock jitter estimation and sign-off methodology development
Experience with on-chip clock sign-off, including clock design guide, 3DIC jitter derating, and multi-corner/process variation analysis.
Skills Required
- BS or MS in Electrical Engineering, Physics, or a related field
- 8+ years of experience in component- and system-level SI/PI analysis
- Solid understanding of SI/PI fundamentals and methodologies
- Hands-on experience with lab instruments such as VNA, TDR, and real-time oscilloscopes
- Proficient in EDA tools
What We Do
FuriosaAI designs and develops data center accelerators for the most advanced AI models and applications. Our mission is to make AI computing sustainable so everyone on Earth has access to powerful AI. Our Background Three misfit engineers with each from HW, SW and algorithm fields who had previously worked for AMD, Qualcomm and Samsung got together and founded FuriosaAI in 2017 to build the world’s best AI chips. The company has raised more than $100 million, with investments from DSC Investment, Korea Development Bank, and Naver, the largest internet provider in Korea. We have partnered on our first two products with a wide range of industry leaders including TSMC, ASUS, SK Hynix, GUC, and Samsung. FuriosaAI now has over 140 employees across Seoul, Silicon Valley, and Europe. Our Approach We are building full stack solutions to offer the most optimal combination of programmability, efficiency, and ease of use. We achieve this through a “first principles” approach to engineering: We start with the core problem, which is how to accelerate.
