The Role
Lead verification of RISC-V CPU cores at RTL using SystemVerilog/UVM and a mix of dynamic and formal verification. Develop regressions, use simulation and revision-control tools, collaborate across teams to ensure design correctness.
Summary Generated by Built In
At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking an Senior Verification Engineer specialist to join one of our clients' teams that develops RISC-V CPU cores. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.
As a Senior Verification Engineer, you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the specification, using advanced verification methodologies and tools to validate the designs.
Requirements:
- Master or PhD
- English C1
- Industrial experience +8 years
- Proficiency in SystemVerilog and UVM
- Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
- Experience with simulation and simulation tools
- Knowledge of revision control methodology and tools (git, svn)
- Experience in block level and sub-system or top level verification
- Experience with formal and dynamic verification
- Strong problem-solving skills and attention to detail
- Excellent communication and teamwork abilities
Skills Required
- Master or PhD
- English C1
- Industrial experience 8+ years
- Proficiency in SystemVerilog
- Proficiency in UVM
- Knowledge of scripting languages (Python, Perl, Bash, TCL)
- Experience with regression tools
- Experience with simulation and simulation tools
- Knowledge of revision control methodology and tools (git, svn)
- Experience in block level and sub-system or top level verification
- Experience with formal and dynamic verification
- Strong problem-solving skills and attention to detail
- Excellent communication and teamwork abilities
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The Company
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