Job Summary:
We are seeking a Senior Software Engineer to join our R&D team.
In this role, you will be responsible for the design and implementation of advanced solutions,
tackling both algorithmic and performance challenges.
Responsibilities:
Design and implement solutions to complex optimization problems.
Develop and enhance algorithms and software systems..
Optimize existing code and systems for improved performance and scalability.
Identify and correct bottlenecks and fix bugs.
Help maintain code quality, organization, and automation.
Qualifications:
Bachelor's or Master's degree in Computer Science, Engineering, or a related field.
At least 5 years of professional experience in software development.
Strong coding skills in one or more programming languages similar to C++ or Rust.
Capable of writing high-performance code and debug effectively.
Ability to think out of the box and provide innovative solutions.
Strong learning skills and independence.
High-level view of system architecture.
Excellent problem-solving skills and ability to face challenges head-on.
Great human relationships and collaboration skills.
Preferred Qualifications:
Experience in chip design or verification.
Skills Required
- Bachelor's or Master's degree in Computer Science, Engineering, or related field
- At least 5 years of professional experience in software development
- Strong coding skills in programming languages similar to C++ or Rust
- Ability to write high-performance code and debug effectively
- Excellent problem-solving skills
What We Do
Hiveware is reinventing digital chip verification by building a high-performance simulation engine from the ground up — no legacy baggage, just raw speed and modern engineering. Hiveware delivers a next-generation RTL/SystemVerilog simulator designed to dramatically reduce simulation runtimes, especially for large, complex SoCs that traditionally require emulation or FPGA prototyping. By rethinking core algorithms and leveraging modern compiler techniques, Hiveware enables faster iteration, higher throughput, and deeper coverage — helping chip teams validate designs earlier and more efficiently. We're not optimizing around the past. We're building the future of EDA.
