Senior Physical Design Engineer

Senior Physical Design Engineer

Mission: build high-performance, power-efficient chips for AI applications.  

Responsibilities & opportunities in this role:

• Technical Lead for full chip integration activities; drive development and deployment of methodologies for these tasks both internally and with ASIC design partner in leading technology nodes.
• Own and drive the overall Global Clock design including simulations and work closely with ASIC design partner in implementing the Global Clocks. 
• Lead and own Sign-off activities like STA, EMIR, Physical Verification from defining the methodology to running these at block and full chip level.
• Own and drive execution of blocks from Synthesis, P&R to Timing Sign-off, Physical Sign-off and Electrical Sign-off. 
• Collaborate closely with the Microarchitecture/RTL team to help drive PPA improvements and resolve design issues.
• Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approach.

Ideal candidates have/are:

• Ability to build strong relationships
• Good written and oral communication skills; strong technical documentation skills
• Good interpersonal skills; a history of mentoring engineers and interns a huge plus
• Highly self-motivated and directed; self-confidence and self-starter
• Keen attention to detail
• Proven analytical and problem-solving abilities
• Ability to effectively prioritize and execute tasks in a high-pressure environment
• Experience working in a team-oriented, collaborative environment

Qualifications for this role:

• BS in Electrical Engineering or Computer Engineer or related degree required; advanced degrees (MS, PhD) a plus.
• 10+ years of meaningful industry experience and a background in block/top level physical design of high-speed processors (i.e. Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs)
• Proven track record of implementing designs through synthesis, placement, CTS, Routing, Extraction, Timing and Physical/Electrical Verification
• Strong hands on experience in implementing  multi-voltage, multi-clock domain designs
• Expert in different CTS methodologies, global and block level clock distribution
• Strong experience with Static Timing Analysis from defining methodologies to running STA at block and top level. 
• Expert in implementing PD power optimization techniques and have a keen eye to look for power reduction options throughout the PD cycle.
• Strong understanding of timing constraints, timing analysis, power grid design, power analysis (EMIR/di/dt), ECO generation and MCMM STA signoff
• Deep understanding of low power format like UPF/CPF
• Experience in formal equivalency checks, Low Power Rule check and verification.
• Expert in industry standard EDA tools like Cadence Genus/Innovus/Tempus, Synopsys Fusion Compiler/ICC2/Primetime, Ansys Redhawk, Joules/PTPX
• Strong Automation skills using scripting languages like TCL, Python, Perl etc.

Attributes of a Groqster:

• Humility - Egos are checked at the door
• Collaborative & Team Savvy - We make up the smartest person in the room, together
• Growth & Giver Mindset - Learn it all versus know it all, we share knowledge generously
• Curious & Innovative - Take a creative approach to projects, problems, and design
• Passion, Grit, & Boldness - no limit thinking, fueling informed risk taking

If this sounds like you, we’d love to hear from you!

Compensation: At Groq, a competitive base salary is part of our comprehensive compensation package, which includes equity and benefits. For this role, the base salary range is $181,700 to $365,400, determined by your skills, qualifications, experience and internal benchmarks.