Senior HW Engineer – PCB Layout

Posted 4 Days Ago
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Oxford, MS, USA
Hybrid
Senior level
Artificial Intelligence • Hardware • Machine Learning • Semiconductor
The Role
Own dense, high-layer-count PCB layout from schematic handoff through fabrication release. Develop stackups, HDI structures, controlled-impedance routing, differential pairs, BGA breakouts, libraries, design rules, and manufacturing documentation. Translate SI/PI constraints into layout rules, conduct DFM/DFA/DFT reviews, manage revisions, and coordinate with fabricators and assembly houses. The role requires expert Cadence Allegro or equivalent Altium experience, production-proven high-speed board design, IPC knowledge, and advanced HDI and fine-pitch package expertise.
Summary Generated by Built In
The Opportunity

Lumai's optical engine only works if the electronics around it hold up. Our boards carry large FPGAs and custom ASICs, multi-gigabit links and fine-pitch packages, and they have to be laid out to tolerances that leave no room for guesswork. This role takes the designs coming out of our hardware and SI/PI teams and turns them into manufacturable, high-layer-count boards.

The Role

You will own board layout from schematic handoff to fabrication release. That covers stackups and HDI structures, controlled-impedance routing, differential pairs, length and phase matching, BGA breakout for large fine-pitch devices, and the full manufacturing package: Gerber/ODB++, drill files, assembly drawings and fabrication notes. You will also own the footprint and symbol libraries, the design rules and the CAD standards the rest of the team works to.

What is genuinely hard about it is that the constraints are real and they conflict. Signal integrity, power integrity, thermal and mechanical requirements all land on the same square centimetres, and the fabricator's process limits decide what is actually buildable. You will be the person who turns simulation output into layout rules and who can defend a stackup to a fabricator.

By month six, you will have taken at least one board through to fabrication release, set the libraries and design rules the team works from, and be the first point of contact for our fabricators and assembly houses.

What You'll Do
  • Lay out dense, high-layer-count PCBs from schematic through to fabrication release, using constraint-driven flows.

  • Implement controlled-impedance routing, differential pair and length/phase matching, and HDI structures including microvias, via-in-pad and back-drilling.

  • Plan BGA breakout and component placement for large FPGAs, custom ASICs and fine-pitch packages, balancing SI, PI, thermal and mechanical requirements.

  • Translate SI/PI and hardware constraints into layout rules, and iterate quickly with engineers on simulation feedback.

  • Run DFM, DFA and DFT reviews, and act as the main technical contact with PCB fabricators and assembly houses.

  • Generate complete manufacturing outputs (Gerber/ODB++, drill files, assembly drawings, fabrication notes) and manage design revisions.

  • Own and maintain the footprint and symbol libraries, CAD standards and design templates, compliant with IPC standards.

What We're Looking For

Must-have
  • Extensive professional experience laying out complex, high-speed, high-layer-count boards, with a portfolio of designs that went into production.

  • Expert proficiency in Cadence Allegro, including Constraint Manager. Equivalent Altium experience will also be considered.

  • Hands-on experience with HDI technologies: microvias, via-in-pad, stacked and staggered vias, and back-drilling.

  • Proven BGA breakout and placement for large, fine-pitch devices such as FPGAs and ASICs.

  • Thorough working knowledge of IPC standards (IPC-2221, IPC-7351, IPC-6012) and of DFM/DFA/DFT principles.

Strong preference for
  • Boards carrying 56G+ SerDes, PCIe Gen5/6 or DDR5 interfaces.

  • Working closely with SI/PI simulation engineers.

  • Rigid-flex, RF or mixed-signal layouts.

  • ECAD/MCAD collaboration on thermal and mechanical integration.

  • Experience setting up CAD standards, libraries and design templates in a growing team.

About Lumai

Lumai is the optical compute company building the next generation of AI infrastructure. Spun out of optics research at the University of Oxford in 2021, we compute with light instead of electrons. Our 3D optical technology carries out the matrix multiplications at the heart of AI inside beams of light travelling through free space, which lets it go beyond the limits of both silicon GPUs and integrated photonics.

In April 2026 we launched Iris Nova, the world's first optical computing system to run billion-parameter large language models in real time, using up to 90% less energy than conventional GPU-based systems. Iris Nova, the first server in the family, is now available for evaluation by hyperscalers, neoclouds, enterprises and research institutions. Aura and Tetra will follow.

Our work won the Falling Walls Award for Science Breakthrough of the Year 2025 and 'Best Overall Technology' at the OCP Future Technologies Symposium. We are headquartered in Oxford.

Why Lumai

You'll work on a new kind of computer. Optical computing for AI has been promised for decades. We have a working system running real models, and the hard part left is taking it to volume.

Your work ships. We are moving from first product to volume production, so what you build this year goes into the servers our customers run.

You'll work across disciplines. Optical engineers, machine learning researchers, and hardware and software engineers solve problems together. You will learn things that don't appear on your job description.

The work matters beyond Lumai. AI's appetite for energy is one of the defining constraints of the next decade. Our mission is sustainable intelligence at global scale: AI that is faster, cheaper to run and far less power-hungry.

You'll join early. You'll have a real say in how we build the product, the team and the way we work.

Equal Opportunity

Lumai is an equal opportunity employer. We make hiring decisions based on skills, experience and potential, and we welcome applications from people of all backgrounds. If you need an adjustment at any stage of the hiring process, let us know and we will do our best to support you.

Skills Required

  • Extensive professional experience laying out complex, high-speed, high-layer-count boards with production designs
  • Expert proficiency in Cadence Allegro, including Constraint Manager; equivalent Altium experience considered
  • Hands-on experience with HDI technologies, including microvias, via-in-pad, stacked and staggered vias, and back-drilling
  • Proven BGA breakout and placement experience for large, fine-pitch FPGAs and ASICs
  • Thorough working knowledge of IPC-2221, IPC-7351, IPC-6012, and DFM/DFA/DFT principles
  • Experience with 56G+ SerDes, PCIe Gen5/6, or DDR5 interfaces
  • Experience working closely with SI/PI simulation engineers
  • Experience with rigid-flex, RF, or mixed-signal layouts
  • ECAD/MCAD collaboration on thermal and mechanical integration
  • Experience establishing CAD standards, libraries, and design templates
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The Company
Year Founded: 2022

What We Do

Lumai is an optical compute company building the next generation of AI infrastructure for the inference era. By utilizing 3D optical computing, the company develops energy-efficient AI processors that surpass the limitations of silicon-based architectures, delivering significantly higher performance and lower power consumption to unlock sustainable intelligence at scale.

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