We are seeking a Senior FPGA Soft IP Development Engineer to own the architecture, micro-architecture, and parameterizable RTL design of high-performance soft intellectual property (IP) blocks. In this role, you will be responsible for developing critical system-level IP cores—including advanced AMBA AXI Interconnect IP - ensuring their portability, scalability, and timing closure across diverse FPGA architectures.
Responsibilities
- Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic, and system interfaces
- Collaborate closely with the verification team to shape test plans and improve verification coverage
- Work with the physical design team to understand and resolve timing, power, and congestion challenges
- Work with the verification team on regression failure debug and root cause, and provide RTL fixes if necessary
- Provide technical support to the FAE team on pre-sales customer engagements
- Provide technical support to the AE team on post-sales customer deliveries
- Apply working knowledge of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis within the design flow
- Develop RTL micro-architecture from scratch
- Provide technical guidance and mentorship to other engineers while remaining a hands-on individual contributor
Required Qualifications & Technical Skills
- Education & Experience: bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5+ years of dedicated RTL/FPGA design experience.
- Protocol Expertise: Deep, hands-on knowledge of the AMBA AXI4 protocol suite and high-speed memory interfaces.
- Toolchains: Proficiency with FPGA implementation tools and EDA simulation software (Siemens Questa/Modelsim, Synopsys VCS).
- Scripting: Strong scripting skills in Python, Tcl, or Perl for build automation and test automation.
Skills Required
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field
- 5+ years of dedicated RTL/FPGA design experience
- Deep, hands-on knowledge of the AMBA AXI4 protocol suite
- Experience with high-speed memory interfaces
- Proficiency with FPGA implementation tools and EDA simulation software, including Siemens Questa/ModelSim and Synopsys VCS
- Strong scripting skills in Python, Tcl, or Perl for build and test automation
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
Altera (altera.com) Insights
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
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