Senior FPGA Design and Verification Engineer

Responsibilities:

• FPGA Design and Development:
• Architect and design FPGA-based systems to meet project requirements.
• Implement and optimize FPGA designs for performance, power, and area efficiency.
• Collaborate with hardware and software teams to integrate FPGA solutions into larger systems.
•  Verification and Testing:
• Develop and execute comprehensive test plans to ensure the reliability and functionality of FPGA designs.
• Debug and troubleshoot FPGA designs, identifying and resolving issues in a timely manner.
•  Documentation:
• Generate clear and comprehensive documentation for FPGA designs, including specifications, test plans, and user guides.
• Maintain version-controlled design documentation throughout the development lifecycle.
• Team Leadership:
• Provide mentorship and guidance to junior FPGA engineers.
• Collaborate with cross-functional teams to ensure seamless integration of FPGA solutions.
• Research and Innovation:
• Stay abreast of industry trends and emerging technologies in FPGA design.
• Explore and recommend new tools, methodologies, and techniques to enhance FPGA development processes.
• Project Management:
• Work closely with project managers to define project milestones, deliverables, and timelines.
• Contribute to project planning and resource allocation for FPGA development activities.

Qualifications

• Experience:
• Minimum of 6 years of hands-on experience in FPGA design and development.
• Experience in the FPGA based 5G Wireless systems and/or ORAN Fronthaul technology will represent a plus.
• Proven track record of successfully delivering complex FPGA projects from concept to production.
• Technical Skills: 
• Strong understanding of high-speed digital design and signal integrity principles.
• Expertise of RTL optimized design technique in digital and DSP domain with Verilog/SystemVerilog and/or VHDL.  
• Proficient in using FPGA design-verification tools from vendors such as Xilinx/AMD or Altera/Intel, simulator  Questasim.
• Knowledge of FPGA’s synthesis, place-n-route process, and optimization for timing closure techniques. 
• Familiar with FPGA interfaces – 10/25/100GbEth, ADC/DAC, uART, SPI, I2C, DDR4, JESD204B, PCIe.
• Ability to write module-level and/or top-level FPGA testbench with testcases to ensure the design coverage in simulation. 
• Lab troubleshooting skills - mastering the lab set up, equipment and leveraging FPGA’s chipscope (or signaltap) debug tool. 
• Knowledge of at least one between bash and Python scripting language.
• Proficiency with C programming language.
• Skills that are not mandatory but that will be considered a plus:
• Proficiency with Linux systems, both as development environments and as FGPA embedded OS. This is a very strong plus.
• Other languages considered a plus are tcl, Makefile.
• Familiarity with bitbucket, Jira-based workflow is a plus.
• Familiarity with Jenkins framework and groovy language is a plus.
• Knowledge of FPGA security embedded systems, including ORAN Fronthaul’s vulnerability security WG11, secure boot, and MACsec.