Senior Digital IC Architect

ABOUT ARAGO

The demand for more intelligence continues to accelerate in every industry, application, and device. Yet, general-purpose processors, cannot take us much farther. To unlock the next breakthroughs, Arago is developing a processor that harnesses the unique physical properties of light to address both memory and computational limitations.

We are a team of AI engineers and physicists who believe in great science and fast achievements. We’re looking for bold jack-of-all-trades who love to ship products quickly.

Our team is driven by these core values:

1. Do great things : We’re going after a 10x, not 10%. It requires intensity, craftsmanship and great science

2. We move as one : Our relationships are built on trust and mutual admiration. We feel empowered and fortunate to collaborate with one another.

3. Keep looking ahead : Lasting technologies and impactful ventures are not built overnight. We take it one step at a time, with velocity.

OVERALL MISSION

Be the inaugural member of our Digital IC team, taking ownership of defining, designing, and implementing the digital subsystems in advanced mixed-signal ICs.

DESIRED SKILL SET

• Proven experience in designing digital circuits and subsystems for mixed-signal ICs.

• Strong understanding of digital signal processing concepts, including filtering, error correction, and clock synchronization.

• Proficiency with Cadence for the complete digital IC flow—RTL design, synthesis, place and route, timing analysis, and sign-off.

• Solid experience coding in Verilog/SystemVerilog. Ability to write high-quality, reusable, and scalable RTL code.

• Experience integrating and verifying high-speed serial/parallel interfaces (e.g., SERDES, SPI, I2C, parallel bus architectures).

• Familiarity with high-speed memory interfaces (HBM) or other standard interfaces is highly valued.

• Good understanding of how analog/RF front-ends interface with digital blocks, including knowledge of noise considerations and signal integrity.

MISSIONS & RESPONSABILITIES

• Take ownership of the digital subsystem architecture for the mixed-signal ICs, defining data paths, control logic, and interfaces to analog/RF blocks.

• Drive the definition and partitioning of the system at block and chip levels in collaboration with analog and RFIC engineers.

• Evaluate, select, and integrate third-party and internally developed IP cores (e.g., SERDES, high-speed parallel interfaces).

• Design and implement error correction logic (ECC, CRC, etc.) to maintain data integrity at high speeds.

REWARDS & PERKS

• Competitive cash compensation that reflects your expertise and experience.

• Stock options.

• Ownership of a key technical area.

• Being part of the very early days of one of the hottest AI startups (still in stealth mode).

• A fun, dynamic, and multicultural team in a collaborative work environment.

• Exciting growth opportunities.

SELECTION PROCESS

1. CV and technical project reviews.

2. 45-minute call with the CEO.

3. Take-home technical assignment.

4. 1-hour technical call with the CTO, CSO, CEO and potential other team members.