Senior ASIC Design Engineer

Posted 3 Days Ago
Be an Early Applicant
2 Locations
Remote or Hybrid
Senior level
Software
The Role
The candidate will automate ASIC design workflows, develop and maintain RTL IP modules, and improve methodologies for design efficiency in a high-impact environment.
Summary Generated by Built In

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

 Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.
Work as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market.
 

Responsibilities

As a member of the ASIC design team, you will play the role to automate cad flows for ASIC design

The candidate:
Develops and maintains key common RTL IP modules used at every product generation 

  1. Interacts with RTL designers to understand the flow of work, develops the architecture to automate the flow and then implements the automation to eliminate pain points and errors to de-risk projects.
    2.Develop Synthesis flows and run synthesis along side with other designers and provide feedback to designers to improve timing and power.
    3. Develops scripts to automate using Python, Perl or other scripting languages. 
    4. Works as part of a methodology team to develop new CAD/methodologies or flows which improve quality of design, reduce design time and provide consistent and reliable results across users and sites and streamline the process of ASIC development.
    5. Identifies input variables, categorizing them as fixed or customizable or user controllable options allowing users to have simplified interaction with the tool flow. 
    6. Identifies scope for improvement in existing flows and implement those improvements.
    7. Work with experts and users across sites to identify new methodologies for development and adoption.
    8. Works with EDA tool vendors to identify options available across tools which reduce debug and development effort. Takes the options and make them available in a simplified way to design engineers.
    9. Works with EDA tool vendors to evaluate new tools and new features.
    Develops flows, take it through a proof-of-concept on a project and release the flow for production use across teams and sites.
    10. Makes presentations to teams to ramp users about improvements or new flow development.
     

Works on EDA tool installation and support, compute platform support, LSF job submittal support, infrastructure related support for worldwide ASIC design community.  Works closely with IT and debug and implement solutions.  Continuously monitor/improve CAD infrastructure efficiency and CAD automation. 
The job is a high visibility job and has the potential to improve and impact the work of multiple engineers across geographies.
 

Qualifications
  1. Hold a Bachelor or master’s degree in electrical or computer engineering

  2. Have a minimum 5 years of experience with relevant experience

  3. Have a minimum 2 years of RTL design experience 

  4. Strong experience in Synthesis, STA and constraints development

  5. Strong working experience of Shell, Perl, TCL and other programming/scripting language

  6. Strong problem-solving skills

  7. Good verbal/written communication skills and teamwork

  8. Knowledge of Synopsys Electronic Design Automation (EDA) tools an asset

  9. Knowledge of Verilog or System Verilog 

  10. Knowledge of LSF 

  11. Knowledge of machine learning and/or neural networks may be an asset
     

Skills Required

  • Bachelor or master's degree in electrical or computer engineering
  • Minimum 5 years of relevant experience
  • Minimum 2 years of RTL design experience
  • Strong experience in Synthesis, STA, and constraints development
  • Strong working experience of Shell, Perl, TCL
  • Knowledge of Synopsys EDA tools
  • Knowledge of Verilog or System Verilog
  • Knowledge of LSF
  • Knowledge of machine learning and/or neural networks

Nokia Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Nokia and has not been reviewed or approved by Nokia.

  • Equity Value & Accessibility Equity programs include a global employee share purchase plan with company matching and multi‑year share awards. These mechanisms broaden participation and tie rewards to long‑term outcomes.
  • Healthcare Strength Health coverage includes major medical plans with supplementary options such as vision, legal services, and care navigation. The range of offerings indicates comprehensive support for medical needs.
  • Parental & Family Support A global policy grants paid leave for new parents regardless of gender and provides structured return‑to‑work support. Company‑paid life insurance further strengthens family protection across regions.

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The Company
Dallas, Texas
132,624 Employees

What We Do

At Nokia, we create technology that helps the world act together. As a trusted partner for critical networks, we are committed to innovation and technology leadership across mobile, fixed and cloud networks. We create value with intellectual property and long-term research, led by the award-winning Nokia Bell Labs. Adhering to the highest standards of integrity and security, we help build the capabilities needed for a more productive, sustainable and inclusive world.

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