ASIC Design Engineer

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Adtran Sweden is a development organization based in Stockholm that develops integrated circuits (ASIC) for use in Adtran’s networking products. Adtran Sweden also develops SW drivers and software development tools (compiler, debugger and simulator) to support application development for the Adtran ASICs. The organization manages all aspects of ASIC development from product definition, architecture design, functional design, verification, physical implementation and release to manufacturing.

In preparation for new projects, Adtran looks to extend the ASIC team. We search for ASIC designers that has started a career and wants to learn this demanding and complex domain. The right candidate has a burning interest in ASIC design and wants to become part of a top class ASIC team that develops very large, complex ASICs. New members will work closely with the team in Stockholm.

Responsibilities

An ASIC Designer develops the micro architecture and the functionality of the IC. This requires close interaction to architects and fellow ASIC designers. The interface to architects is at a high level of abstraction, thus the designer must be able to understand the architecture of a networking IC device and define and implement the functionality in an hardware description language, System Verilog or VHDL. The ASIC designer works closely with an ASIC Lead Designer who manages the micro architecture and the design specification.

An ASIC designer needs to interact with verification engineers for functional verification and backend engineers for physical implementation. This requires familiarity with the entire ASIC design flow. The work model will be a mixture between remote work from a local Adtran office and regular travels for face to face work with the team in Stockholm.

Qualifications

Digital Design Expertise

• Thorough understanding of digital logic design concepts: combinational logic, sequential circuits, finite state machines, pipelining, etc.

• Experience in Verilog and/or System Verilog.

• Familiarity with timing optimization, area and power tradeoffs.

• Familiarity integrating third-party or internally developed IP blocks is a benefit.

• Familiarity with standard bus protocols (AMBA: AXI/AHB/APB, PCIe, etc.) is a benefit.

ASIC Design Flow Knowledge

• Familiar with RTL synthesis and timing analysis (STA)

• Knowledge of back-end flow (optional but valuable): place & route (P&R), DRC/LVS, physical design constraints.

EDA Tool Proficiency

• Experience with tools such as:

  • Synthesis: Synopsys Design Compiler, Cadence Genus

  • Simulation: ModelSim, VCS, Xcelium

  • STA: PrimeTime, Tempus

  • Linting & CDC: SpyGlass, Conformal, Questa CDC

Compensation and Benefits (site in Poland)

• Stable employment conditions based on an employment contract (turnover rate below 4%)

• 1 additional vacation day for all, and 1 extra after 10 years being with us

• Flexible working hours and hybrid work (presence in the office in Gdynia 3 days a week)

• English lessons during working hours

• Internal training program to support your training needs

• Paid employee referral program

• Multisport Card

• 3% employer contribution to PPK

• Private Health Care at Medicover (extended package for employees and possibility to enroll family members)

• Strong collaborative and friendly work culture

• Access to various sports activities and events

• Modern office (well-equipped gym and playroom) close to the SKM/PKM stations