Principal Microelectronics Architect

Remote (U.S.) | Full-Time | Secret Clearance Required

Position: Principal Microelectronics Architect (SME)
Location: Remote (Periodic On-site Support as Needed)
Category: Hardware Engineering / Systems Architecture
Clearance Requirement: U.S. Citizenship Required; Active Secret Clearance
Education Requirement: Bachelor's Degree in Electrical Engineering, Computer Engineering, or related discipline (Master's or PhD preferred)
Experience Requirement: 10+ Years in Microelectronics Design, Semiconductor Development, or IP Architecture

We are seeking an experienced Principal Microelectronics Architect to serve as a Subject Matter Expert (SME) supporting a critical government-sponsored microelectronics modernization initiative. This role will provide technical leadership in the development of a secure, collaborative design environment focused on advancing semiconductor innovation, intellectual property reuse, and next-generation design workflows.

The selected candidate will work within a highly technical team responsible for defining architecture, standards, and governance models that support the development and integration of advanced microelectronics technologies. This position offers the opportunity to influence long-term strategy while working closely with government stakeholders, industry partners, and engineering teams across the semiconductor ecosystem.

The ideal candidate brings deep expertise in microelectronics design, silicon IP, system-on-chip (SoC) architecture, FPGA technologies, and semiconductor design workflows, along with the ability to communicate complex technical concepts to both technical and executive audiences.

• Serve as a trusted technical advisor supporting the development of secure, cloud-enabled microelectronics design environments.
• Provide expertise in semiconductor design methodologies, silicon IP reuse, and design ecosystem modernization.
• Guide architectural decisions that support long-term scalability, interoperability, and sustainability.

• Develop and validate standards for managing reusable design IP repositories.
• Establish best practices for secure integration and lifecycle management of commercial and government-developed IP assets.
• Assess technical risks, licensing considerations, and long-term sustainability of IP portfolios.
• Support governance strategies that promote efficient IP sharing and collaboration.

• Evaluate and optimize semiconductor design workflows across modern engineering environments.
• Support the integration of foundry-qualified design flows and advanced packaging technologies.
• Promote interoperability across multiple vendors, toolchains, and semiconductor platforms.
• Identify opportunities to accelerate development timelines and improve engineering productivity.

• Conduct technology evaluations and produce technical assessment reports.
• Deliver recommendations related to design infrastructure, tool interoperability, and ecosystem scalability.
• Support milestone reviews and provide technical briefings to program leadership and stakeholders.
• Contribute to strategic roadmaps that support future program growth and modernization efforts.

• Coordinate requirements and technical activities across government organizations, industry partners, research institutions, and engineering teams.
• Facilitate collaboration among stakeholders focused on semiconductor design, fabrication, packaging, and testing.
• Build consensus around standards, processes, and technical direction.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline
• 10+ years of experience in microelectronics design, semiconductor development, FPGA design, or System-on-Chip (SoC) architecture
• Deep understanding of silicon IP development, integration, validation, and reuse methodologies
• Experience evaluating and managing third-party intellectual property within complex hardware environments
• Familiarity with industry-standard Electronic Design Automation (EDA) tools, including:
  • Cadence
  • Synopsys
  • Siemens EDA
• Understanding of cloud-enabled design environments and collaborative engineering workflows
• Strong knowledge of semiconductor design processes and technology development lifecycles
• Exceptional technical writing, documentation, and presentation skills
• Ability to communicate complex technical concepts to both engineering teams and executive leadership
• U.S. Citizenship with the ability to obtain and maintain a Secret security clearance

• Active Secret clearance or higher preferred
• Experience supporting government-sponsored microelectronics programs
• Familiarity with trusted semiconductor manufacturing and supply chain assurance initiatives
• Experience with advanced packaging technologies and chiplet architectures
• Knowledge of modern semiconductor fabrication processes and foundry ecosystems
• Familiarity with radiation-hardened, high-reliability, or mission-critical electronics
• Experience supporting collaborative research and development initiatives involving government, industry, and academia
• Knowledge of leading semiconductor foundries and advanced process technologies

TAP Engineering offers a comprehensive and highly competitive benefits package designed to support your health, financial well-being, professional growth, and work-life balance.

• Paid Time Off: 15–25 days of PTO annually based on tenure, plus 11 paid holidays with no use-it-or-lose-it policy.
• Retirement Benefits: Up to a 15% employer contribution to your 401(k) through a combination of company match and profit-sharing.
• Comprehensive Medical Coverage: Employer-paid medical insurance for employees, with optional enhanced plans and dependent coverage available.
• Dental & Vision Insurance: Employer-paid dental and vision coverage with optional buy-up plans.
• Tuition Reimbursement: Up to $36,000 annually for approved degree programs, certifications, and continuing education opportunities.
• Wellness & Employee Support Programs: Employee Assistance Program (EAP), wellness incentives, virtual healthcare services, prescription savings programs, and travel assistance resources.
• Additional Employee Perks: Access to employee discount programs and other company-sponsored benefits.
• Performance-Based Recognition: Merit increases, performance bonuses, and employee referral bonuses designed to reward contributions and success.

This is a unique opportunity to help shape the future of microelectronics design and collaboration within a highly visible national-level initiative. You'll work alongside industry and government leaders, influence next-generation design environments, and contribute to the development of technologies that will impact critical systems for years to come.

The role begins with an initial six-month technical engagement focused on architecture definition, standards development, and technology assessments. Successful completion of Phase 1 is expected to lead to a five-year follow-on effort, providing the opportunity to serve as a technical lead for a major microelectronics modernization initiative and help shape its long-term architecture, standards, and implementation strategy.