Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Logic Design Engineer – UALink IP/Subsystem
Experience
10–15 years
Job Summary
We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems.
Key Responsibilities
- Lead architecture and RTL development for UALink IP/subsystems.
- Translate protocol and system requirements into scalable hardware architecture.
- Design high-bandwidth, low-latency data paths and control logic.
- Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Define interfaces between UALink and other SoC/interconnect components.
- Develop and review SystemVerilog RTL.
- Drive design optimization for performance, power, area, and latency.
- Work closely with verification, physical design, SoC integration, and firmware teams.
- Review design specifications and contribute to architectural decisions.
- Debug complex simulation and integration issues.
- Provide technical leadership and mentorship.
Required Skills
- Strong experience in RTL and microarchitecture development.
- Experience with high-speed interconnects and/or coherent fabrics.
- Strong understanding of computer architecture, networking/interconnect concepts, and data movement.
- Proficiency in SystemVerilog/Verilog.
- Strong understanding of CDC, reset architecture, performance, and hardware design methodology.
Preferred
- Direct UALink experience.
- Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
- Experience in AI/accelerator or high-performance compute systems.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- 10–15 years of experience
- Strong experience in RTL and microarchitecture development
- Experience with high-speed interconnects and/or coherent fabrics
- Strong understanding of computer architecture, networking/interconnect concepts, and data movement
- Proficiency in SystemVerilog and Verilog
- Strong understanding of CDC, reset architecture, performance, and hardware design methodology
- Direct UALink experience
- Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols
- Experience in AI/accelerator or high-performance computing systems
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
