Principal IC Implementation / STA AE

Posted 2 Hours Ago
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Austin, TX, USA
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Provides pre-sales and post-sales technical support for Cadence digital implementation and signoff tools. Delivers customer workshops, benchmarks, demonstrations, methodology consultations, technical evaluations, and implementation support. Partners with sales teams on technical campaigns, supports customer usage expansion, collaborates with R&D on tool improvements, and creates technical content. Requires expertise in static timing analysis, advanced-node design closure, ASIC implementation flows, constraints debugging, UPF, hierarchical and 3DIC STA, and scripting.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.


Job Description

We are looking for a Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. The candidate will work closely with sales executives in supporting sales campaigns by delivering workshops, benchmarks, product demonstrations, methodology consultations and product support. 


Position also involves:

•    Presenting to customers the technical capabilities of Cadence Digital Implementation and Signoff tools and flows (Synthesis, Place and Route, Timing/Physical/Power Signoff).

•    Recognizing opportunities for products at existing customers or potential customers, and working with account team to define and execute technical campaigns

•    Support technical evaluations/benchmarks and drive the process to deliver Cadence solutions implementations

•    Ongoing support and usage proliferation at existing customers (on/offsite)

•    Working closely with R&D on tools and methodology improvements

•    Create and contribute technical content for Cadence Online Support

•    Travel as required (up to 20%)


The Position Requirements are…

  • Minimum BS-EE plus 8 to 10 year’s experience or MS-EE, plus 6 to 8 year’s experience, Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
  • Digital Design Fundamentals, Semiconductor fundamentals and  Static Timing Analysis is required
  • Experience with ASIC digital implementation flows and tools
  • Working knowledge of a scripting language TCL/Perl/Python
  • Candidate should have strong customer-facing communication and problem solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Strong verbal and written communication skills
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor of Science in Electrical Engineering with 8 to 10 years of experience
  • Master of Science in Electrical Engineering with 6 to 8 years of experience
  • Core timing signoff expertise
  • Advanced-node static timing analysis experience
  • UPF and constraints debugging experience
  • Hierarchical and 3DIC design static timing analysis and closure solutions experience
  • Digital design fundamentals
  • Semiconductor fundamentals
  • Static timing analysis experience
  • Experience with ASIC digital implementation flows and tools
  • Working knowledge of Tcl, Perl, or Python
  • Strong customer-facing communication and problem-solving skills
  • Strong verbal and written communication skills
  • Commitment to continuous learning and expanding professional skills

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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