We are a company building custom ARM-based hardware to safety-critical standards of reliability and security. We design and build our own boards, not integrate someone else's.
You will be our founding hardware hire — the person who makes the hardware real: silicon selection, board architecture, schematic, layout, power, EMC, bring-up, and design for manufacture and test, in a domain where reliability and security are the product, not features. You'll work alongside our established in-house firmware team.
What you will own
Board architecture & design
- Silicon selection and board architecture: processor and MCU choices, module-vs-chip-down trade-offs, boot straps, debug topology, connector strategy.
- Schematic capture and PCB layout end to end: component selection with lifecycle and second-source awareness, multi-rail power-tree design and sequencing, clock distribution, reset architecture, stackup planning with the fab.
- High-speed digital done correctly: impedance control, length matching, return paths, SI/PI budgets for interfaces like Gigabit Ethernet, PCIe, USB, and memory.
- Design for demanding environments: derating, worst-case analysis, thermal, protection circuits, and EMC/EMI pre-compliance from rev A rather than as a rescue.
Bring-up, validation & manufacture
- Lead bench bring-up: first power-on, rail and sequencing checkout, clock/reset verification, interface validation with scope, logic analyzer, and JTAG.
- Build the validation story: designed-in test points, bring-up checklists, test fixtures, and a path to production test (ICT/flying-probe/functional).
- Own DFM/DFT and the fab/assembly relationship: panelization, BOM health, alternates, revision discipline from rev A to production.
Reliability, security & safety by design
- Reliability as a design input: schematic-level FMEA, single-point-of-failure analysis, watchdog/supervision circuits, brown-out behavior, graceful degradation.
- Hardware support for security architecture: secure elements, debug-port lockdown, tamper considerations, clean separation of trust domains on the board.
- Regulated-domain discipline — traceability, evidenced design reviews, worst-case and derating analysis — so future certification (ISO 26262, IEC 61508, DO-254, EN 5012x) is a gap analysis, not a redesign.
AI-accelerated engineering
- Use Claude Code as a core instrument: automating BOM and netlist checks, design-rule and review checklists, datasheet digestion, test-plan and bring-up-script generation, documentation — while owning every design decision that ships.
- Build the team's playbook (skills, CLAUDE.md conventions, guardrails) so AI tooling accelerates safety-critical hardware work without compromising rigor.
What we need to see
Required
- Designed and shipped multiple custom (non-devkit) digital boards as the responsible engineer — schematic and layout — including at least one embedded Linux-class board around silicon from a major ARM vendor: NXP, ST, TI, Renesas, Microchip, or similar.
- Proven high-speed digital competence: impedance-controlled routing, length matching, SI awareness for interfaces like Gigabit Ethernet, PCIe, or USB 3 — with boards that passed EMC on an early rev.
- Strong power-integrity and power-tree design: multi-rail PMIC-based designs, sequencing, and the analysis to prove margins rather than hope for them.
- Owns bring-up personally: methodical bench debugging with scope, logic analyzer, and JTAG.
- Shipped hardware under a functional-safety or airworthiness regime: ISO 26262, DO-254/DO-160, IEC 61508, EN 50126/50129, or IEC 61513/60880.
- Demonstrably expert with Claude Code — real workflows applied to hardware engineering, not just chat usage.
Skills Required
- Designed and shipped multiple custom, non-development-kit digital boards as the responsible engineer, owning schematic and layout.
- Designed at least one embedded Linux-class board using silicon from a major ARM vendor such as NXP, ST, TI, Renesas, or Microchip.
- Demonstrated high-speed digital design expertise, including impedance-controlled routing, length matching, signal-integrity awareness, and interfaces such as Gigabit Ethernet, PCIe, or USB 3.
- Shipped boards that passed EMC testing on an early revision.
- Designed multi-rail PMIC-based power trees with sequencing and margin analysis.
- Personally led hardware bring-up and bench debugging using an oscilloscope, logic analyzer, and JTAG.
- Shipped hardware under a functional-safety or airworthiness regime such as ISO 26262, DO-254/DO-160, IEC 61508, EN 50126/50129, or IEC 61513/60880.
- Demonstrated expert-level Claude Code usage through real hardware-engineering workflows.
Alphapoint Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Alphapoint and has not been reviewed or approved by Alphapoint.
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Leave & Time Off Breadth — Unlimited PTO and flexible schedules enable people to take the time needed to recharge. Policies are framed to accommodate personal priorities beyond a traditional 9-to-5.
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Healthcare Strength — Comprehensive medical, dental, and vision coverage is paired with life insurance and short- and long-term disability. This breadth of protection aims to provide strong health and financial security.
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Retirement Support — A 401(k) plan with employer matching is provided to help build long-term financial security. Retirement support is positioned as a core element of the total rewards package.
Alphapoint Insights
What We Do
Alphapoint provides software infrastructure for institutions operating digital asset businesses. Founded in 2013, Alphapoint began as a white-label exchange technology provider, helping companies launch and operate digital asset trading platforms in live markets. Today, Alphapoint also supports stablecoin treasury workflows, institutional liquidity, and broader digital asset operations for financial institutions, fintechs, payment companies, brokers, and market operators. Alphapoint has served more than 150 customers across 35+ countries and supported more than $1T in platform activity.
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