We are seeking an experienced Analog Design Engineer with 12-18 years of expertise in high-performance PLL and clocking solutions to join our product development team. The candidate will lead the design and development of advanced clock generation, distribution, synchronization, and timing circuits for next-generation SoCs and mixed-signal products, driving innovations from architecture definition through silicon validation and production.
Key Qualifications- 12+ years of experience in analog/mixed-signal IC design with strong expertise in PLL and clocking architectures.
- Deep transistor-level design experience of PLL building blocks including VCOs, charge pumps, phase/frequency detectors (PFDs), loop filters, clock buffers, bandgap references, current references, OPAMPs, and LDOs.
- Strong understanding of jitter, phase noise, clock synchronization, timing recovery, EMC/ESD, reliability, and silicon robustness.
- Hands-on experience with analog design and verification tools such as Cadence Virtuoso, ADE, Spectre/SPICE, and related EDA environments.
- Experience with silicon characterization, validation, yield improvement, and ATE characterization.
- Strong knowledge of advanced CMOS/FinFET technologies and analog layout considerations.
- Proven ability to lead technical reviews, debug silicon issues, and mentor junior engineers.
- Experience with high-speed SerDes, Ethernet PHYs, or timing-intensive mixed-signal systems is an added advantage.
- Architect, design, and verify high-performance PLL, clock generation, clock distribution, and synchronization circuits for advanced semiconductor products.
- Own end-to-end analog design execution including specification definition, transistor-level implementation, performance verification, and silicon bring-up.
- Develop innovative analog circuit solutions to optimize jitter, phase noise, power consumption, and overall system performance.
- Work closely with system, digital, layout, validation, and product engineering teams to define interfaces, calibration methodologies, and verification strategies.
- Drive reliability, EMC/ESD compliance, silicon characterization, and yield improvement activities.
- Lead technical decision-making, conduct design reviews, and provide mentorship to junior engineers while contributing to the overall analog design methodology and roadmap.
More information about NXP in India...
#LI-7013Skills Required
- 12+ years of experience in analog or mixed-signal IC design
- Strong expertise in PLL and clocking architectures
- Transistor-level design experience with VCOs, charge pumps, PFDs, loop filters, clock buffers, bandgap references, current references, OPAMPs, and LDOs
- Knowledge of jitter, phase noise, clock synchronization, timing recovery, EMC/ESD, reliability, and silicon robustness
- Hands-on experience with Cadence Virtuoso, ADE, Spectre/SPICE, and related EDA environments
- Experience with silicon characterization, validation, yield improvement, and ATE characterization
- Knowledge of advanced CMOS/FinFET technologies and analog layout considerations
- Ability to lead technical reviews, debug silicon issues, and mentor junior engineers
- Experience with high-speed SerDes, Ethernet PHYs, or timing-intensive mixed-signal systems
What We Do
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA
