Physical Design Engineer

Posted 2 Days Ago
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Bengaluru, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Information Technology • Professional Services • Consulting
The Role
Perform full-chip and block-level physical design for SoC projects (28nm/14nm+). Responsibilities include synthesis to PnR, floorplanning, placement optimization, CTS, routing, signoff STA, physical verification (DRC/LVS/ERC/antenna) and reliability checks (IR/EM/Xtalk), handling netlist-to-GDSII and timing/functional ECO implementation.
Summary Generated by Built In
Company Description

client of FiniteHR

Job Description

You will be part of a Physical Design team for projects with GHz freq range and cutting edge technologies.

You will be responsible for Physical Design at Full Chip or block level in technologies of 28nm/14nm.

You will be responsible for Synthesis to PnR and Physical Verification closure of SoC/sub-chips.


Desired Skills and Experience:


· B. Tech. / M. Tech. with 5-8 years of experience in Physical Design

· Handled Netlist to GDS II at block level for multiple tape outs

· Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm

· Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC

· Hands-on experience in floorplanning, placement optimizations, CTS and routing

· Hands-on experience in block/top level signoff STA, physical verification(DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk)

· Exposure in physical implementation of timing/functional ECO’s

· Good knowledge of VLSI process and device characteristics

· TCL, perl scripting

Qualifications

· B. Tech. / M. Tech. with 5-8 years of experience in Physical Design

Additional Information

All your information will be kept confidential according to EEO guidelines.

Skills Required

  • B.Tech. / M.Tech. degree with 5-8 years of physical design experience
  • Handled netlist-to-GDSII flow at block level for multiple tape-outs
  • Hands-on experience with technology nodes: 28nm, 20nm, 14nm, 10nm
  • Experience with EDA tools from Synopsys, Cadence, Mentor (ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC)
  • Hands-on floorplanning, placement optimizations, CTS and routing
  • Block/top-level signoff STA and physical verification (DRC/LVS/ERC/antenna) and reliability checks (IR/EM/Xtalk)
  • Exposure to physical implementation of timing/functional ECOs
  • Good knowledge of VLSI process and device characteristics
  • Scripting skills: TCL and Perl
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The Company
0 Employees

What We Do

FiniteHR is a Human Capital Management organization, has been in business since 2014 in Hyderabad, serving IT and non IT clients in Domestic and International markets. They are a team of dedicated professionals with expertise in recruiting professionals and specialized experts across North America, Asia, Middle East and Europe, acting as an ideal outsourcing partner for recruitment and staffing services.

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