Mask Design Engineer

Posted 2 Days Ago
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Hillsboro, OR, USA
In-Office
Senior level
Professional Services • Consulting • Industrial
The Role
Lead mask/layout design for analog and mixed-signal blocks (LDOs, regulators, data converters, PLL, SerDes, LVDS) at 14nm/FinFET nodes. Perform layout, verification (LVS/DRC/DFM/OPC), reliability analysis (EM/IR/ESD), post-layout fixes, full-chip integration, and coordinate with circuit design teams. Use Genesys/Genoa, Cadence and Mentor tools and Apache analysis flows.
Summary Generated by Built In
Company Description

Founded in 2009 and headquartered in Ann Arbor, MI, TEKWISSEN™ provides a unique portfolio of innovative capabilities that seamlessly combines clients insights, strategy, design, software engineering and systems integration. Our tightly integrated offerings are tailored to each client’s requirements and span the services spectrum from Application Development/Maintenance, testing, Technology Consulting & staffing. The company is primarily focused on information technology, engineering, healthcare, financial technology and contingent workforce solutions. It operates in seven business segments including Commercial, Professional & Technical, EMEA Commercial, and EMEA Professional & Technical. The company provides professional and technical expertise in the fields of Telecom, Education, Banking, Retail, e-commerce, Automotive, Life Science, Insurance, legal, healthcare, among others. It also offers outsourcing, consulting, recruitment, career transition, and vendor management services.
We strongly believe:
" If something cannot be measured, it cannot be managed. "
TEKWISSEN™ measures all of these processes and applies corrective interventions to manage the quality process at its core.
We are an Equal Employment Opportunity Employer M/F/V/D
Recognitions:
2015 -America’s Fastest Growing Company by Inc.com
2015- SPARK FastTrack Award from Ann Arbor SPARK
2015 -Honoree of Diversity Focused Company by Corp! Magazine
2014- America’s Fastest Growing Company by Inc.com
2014- Michigan 50 Companies to Watch
2014 – DiSciTech Award in Technology by Corp! Magazine
2014- DiSciTech TECHNOLOGY Company of the year by Corp! Magazine
2014- SPARK FastTrack Award from Ann Arbor SPARK
Specialties:
Enterprise Solutions, Web Development, Data Warehousing, Systems Integration, IT Security, Storage Technologies, Development and Delivery, Business Intelligence, Telecommunications, Consulting and Planning, Network design, Implementation &Administration

Job Description

Mask Design
Location: Hillsboro, OR
Duration: Long Term
Job Description:
Manditory skills:
  
1.      14nm
2.      Genesys, Genoa
3.      Voltage regulators, LDO
•    At least 4 – 8 years’ experience in understanding and Independent handling of various Analog and Mixed Signal blocks such as LDO,  Switching Regulators, Data Converters,  PLL, SerDes, LVDS and top level layout  integration of AMS blocks.
•    Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes like 14nm,22nm, 16nm FinFET technologies
•    Experience in Genesys / Genoa layout editor, Aapr flow, Helix etc  
•    Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
•    Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc using Apache tools
•    Should have good knowledge of CMOS, FinFET process and fabrication
•    Knowledge of scripting languages such as Perl/Tcl and Skill is a plus.
•    Full-chip integration and verification experience
•    Good team player with excellent communication skills, interfacing with the circuit team
-    Layout design, Verification, Post-layout fixes and sign-off of high performance of Analog and Mixed Signal blocks, and IO / High Speed IO blocks
-    Mask Design team lead for the client engagement
-    Interface with the Circuit Design team at Onsite
•    Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) , Hercules 

Additional Information

Regards,
Narendra
734-357-8978
narendra(dot)s(at)tekwissen(dot)com

Skills Required

  • 4-8 years experience in analog and mixed-signal layout and independent handling of blocks (LDO, switching regulators, data converters, PLL, SerDes, LVDS)
  • Experience with 14nm, 22nm and 16nm FinFET CMOS process nodes and deep sub-micron layout techniques
  • Proficiency with Genesys / Genoa layout editor, Aapr flow, Helix
  • Proficiency with industry EDA tools: Cadence (Virtuoso-L, Virtuoso-XL, PVS, QRC), Mentor Graphics (Calibre, XRC), Hercules
  • Strong debugging and physical verification skills: LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC
  • Reliability analysis experience (EM, IR drop, latch-up, ESD) using Apache tools
  • Good knowledge of CMOS/FinFET process and fabrication
  • Full-chip integration and verification experience
  • Mask Design team lead responsibilities and interfacing with onsite circuit design team
  • Knowledge of scripting languages (Perl, Tcl, Skill)
  • Good communication and teamwork skills
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The Company
125 Employees
Year Founded: 2012

What We Do

STEM Xpert is a consulting engineering firm recognized in the engineering industry for its commitment to client service and passion for excellence. The firm provides specialized professional consulting services in the fields of science, technology, engineering, and mathematics (STEM).

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